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Scientists Pave Way For 25nm CPUs

kdawson posted about 6 years ago | from the still-a-ways-to-go dept.

Hardware 82

arcticstoat writes in with word that scientists at the Space Nanotechnology Laboratory at MIT have found a new way of extending Moore's law into the future — they have succeeded in etching a grid of 25nm lines into a silicon wafer. The article notes that this technique could be used for writing the grid on which chips are laid down, but that the electronic elements would have to be written using more complex techniques. "[Researchers] created an interference pattern using light from a laser with a wavelength of 351 nm. The pattern consists of alternating light and dark zones repeating every 200 nm. This allowed them to etch 25-nm lines into a silicon wafer, each 175 nm apart. They then repeated the process three times, each time shifting the interference pattern by 50 nm and etching another 25-nm groove. The resulting grid has alternating 25-nm stripes and grooves..."

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wow - 25nm (0)

Anonymous Coward | about 6 years ago | (#24165521)

Let see - 10Ghz chip running at 1.2V
and my DSL broadband still at 800kbps on a good day.

Re:wow - 25nm (1)

negRo_slim (636783) | about 6 years ago | (#24165531)

I'd buy that for a dollar.

Re:wow - 25nm (1)

WhoBeDaPlaya (984958) | about 6 years ago | (#24165541)

This and the NSL (Nanastructure Lab) do pretty amazing stuff.

Re:wow - 25nm (1)

Grey Ninja (739021) | about 6 years ago | (#24165633)

What on earth is a nanastructure?

Re:wow - 25nm (1)

freeasinrealale (928218) | about 6 years ago | (#24165765)

I'm still trying to figure out what the heck "scientists at the Space Nanotechnology Laboratory at MIT " is?? Are they like...A small lab on the space station??? Huh?

Re:wow - 25nm (2, Informative)

omeomi (675045) | about 6 years ago | (#24165793)

I'm still trying to figure out what the heck "scientists at the Space Nanotechnology Laboratory at MIT " is?? Are they like...A small lab on the space station??? Huh?

er, MIT is a school in Massachusettes. They have a laboratory called the Space Nanotechnology Lab [mit.edu] .

Re:wow - 25nm (1)

freeasinrealale (928218) | about 6 years ago | (#24165821)

Doh!!

Re:wow - 25nm (1)

AllIGotWasThisNick (1309495) | about 6 years ago | (#24165973)

Doh!!

Don't feel bad. "Space" does in fact modify [wikipedia.org] "Laboratory" not "Nanotechnology".

Re:wow - 25nm (1)

K. S. Kyosuke (729550) | about 6 years ago | (#24166327)

That would be "MIT Technology Nanolaboratory in space", I guess.

Re:wow - 25nm (3, Funny)

Anonymous Coward | about 6 years ago | (#24166117)

>What on earth is a nanastructure?

It's your Grandmother's house, of course.

Re:wow - 25nm (1)

ben(zen) (1162093) | about 6 years ago | (#24166969)

>What on earth is a nanastructure?

It's your Grandmother's house, of course.

Indeed, but on what scale?

Re:wow - 25nm (1)

Hucko (998827) | about 6 years ago | (#24169817)

Relative

Re:wow - 25nm (1)

flappinbooger (574405) | about 6 years ago | (#24169939)

Nana... Nanner ... Hmmm, potassium based circuitry? With a dose of fiber? Sounds futuristic!

Re:wow - 25nm (1)

Hojima (1228978) | about 6 years ago | (#24167033)

Actually, there is more innovative stuff that can make computers faster, but people insist on making them smaller. Take the conducting plastics [thefutureofthings.com] that are under development. If they have a much greater chance of making computers faster with less conventional methods, I don't see why they dont use them.

Re:wow - 25nm (1)

hairyfeet (841228) | about 6 years ago | (#24169953)

But isn't the problem not so much the continued shrinking it down,but at such tiny sizes you have a better chance for the electrons leaking? I am not an engineer,but IIRC there have been several articles in the past few years on the need to switch to something besides silicon due to the electrons leaking once you go below a certain size. And how small CAN you get before the electrons begin to jump the gates on a regular basis? Surely there has to be a size limit. Maybe someone here who IS an engineer can enlighten us all.

This is a bad headline title. (4, Informative)

RightSaidFred99 (874576) | about 6 years ago | (#24165549)

25nm is nothing to write home about, companies are already planning for 25nm. What's exciting is that they created a feature that was smaller than the wavelength of the light used to etch it. Had they used 400nm light to create a 45nm feature, would the title have been "MIT breakthrough could lead to 45nm chips!!!"?

Re:This is a bad headline title. (4, Interesting)

Falstius (963333) | about 6 years ago | (#24165953)

Not only did they make features smaller than the wavelength, they did it with a relatively simple and inexpensive setup. It would be interesting to see this combined with the memristor development in an attempt to create very cheap, high density storage or even cooler, hybrid analog/digital computers.

Re:This is a bad headline title. (1)

kestasjk (933987) | about 6 years ago | (#24170207)

But don't inference patterns only create stripes? I don't see how you could create something as intricate as the placing of each transistor using inference patterns.

No X-ray laser yet? (1)

symbolset (646467) | about 6 years ago | (#24166037)

Somebody better get on that if we're getting to 5nm feature size.

Re:This is a bad headline title. (4, Informative)

damouloud (317642) | about 6 years ago | (#24166069)

Well, the fact that they've been creating features smaller than the wavelength of the illuminating light is nothing to write home about either.

Current chips (since at least the 180nm node) are being fabbed this way at all microelectronics fabs all around the world. We already use 193nm light to create features as small as 22nm (using tricks like immersion, double-exposure and OPC)

Graphene (1, Interesting)

Anonymous Coward | about 6 years ago | (#24170847)

This will help us to get into the resolutions which will make graphene come alive for us. After all, its semiconductive properties only begin to happen at scales of 10nm or lower. I'm eagerly awaiting the graphene age to commence.

Re:Graphene (1)

rootooftheworld (1284968) | about 6 years ago | (#24180275)

i'm not sure if its enirely correct, but - Score:0 ? cut the guy some slack.

Re:This is a bad headline title. (1)

Bombula (670389) | about 6 years ago | (#24166077)

I thought quantum interference was a problem with circuits and gates smaller than 40nm, so even the ability to etch the channels won't mean they'll work. Maybe I'm remembering incorrectly - can someone set the record straight?

Re:This is a bad headline title. (1)

digitally404 (990191) | about 6 years ago | (#24171937)

They've been making features smaller than the wavelength of light for almost a decade now using interference lithography, it's nothing new, but it did scare people that Moore's Law would be over sooner than they thought (after all, how would they write features using extreme UV with the materials that have?).

What's interesting is that their interference lithography mask allows them to reach a minimum feature size limit of 25nm for silicon.

Hurray, Moore's Law should continue for another 10 or so years :) (At least, in terms of using silicon... But we're already using other materials (specifically hafnium) [intel.com] to keep going.)

Fine and dandy, but (-1, Offtopic)

Ethanol-fueled (1125189) | about 6 years ago | (#24165587)

Can they play tic-tac-toe in it?

Re:Fine and dandy, but (3, Funny)

Kohath (38547) | about 6 years ago | (#24165833)

I think the only way to win is not to play.

Re:Fine and dandy, but (1)

kjots (64798) | about 6 years ago | (#24169865)

I think a better way to win would be to get the other guy to not play. Maybe a well-timed kick to the groin would do the trick?

Re:Fine and dandy, but (0)

Anonymous Coward | about 6 years ago | (#24172107)

I think the only way to win is not to play.

I think the only way to win is not to play.

Would you like to play a game of chess?

Intel already had 20nm on their roadmap (0)

Anonymous Coward | about 6 years ago | (#24165609)

Or were they just figuring they'll invent it eventually?

Re:Intel already had 20nm on their roadmap (0)

Anonymous Coward | about 6 years ago | (#24165671)

Yes.

Re:Intel already had 20nm on their roadmap (1)

rhyder128k (1051042) | about 6 years ago | (#24165859)

The current reporting on the supposed end to Moore's Law reminds me of the time that I read an explanation of why 640mb would be absolute limit of HD capacity.

Yes... (-1, Troll)

Anonymous Coward | about 6 years ago | (#24165613)

...but will it help keep the Jews off my lawn?

Re:Yes... (-1, Troll)

negRo_slim (636783) | about 6 years ago | (#24165635)

No for that you need a Scarejew [www.noob.us]

But . . . (0)

Anonymous Coward | about 6 years ago | (#24165691)

. . . Can it run Linux?

Re:But . . . (3, Funny)

mkiwi (585287) | about 6 years ago | (#24165735)

This is just the etching process. They currently don't know how to make transistors that small.

So no, it can't run Linux.

Re:But . . . (1)

jones_supa (887896) | about 6 years ago | (#24172183)

Maybe the etching machine will be controlled by Linux.

ASML has roadmap upto 16 nm chips, (2, Informative)

Anonymous Coward | about 6 years ago | (#24165745)

ASML already has working tools for 32 nm litho. 16 nm is planned in next couple of years.
http://www.asml.com

Is the gap closing? (5, Interesting)

Colourspace (563895) | about 6 years ago | (#24165767)

Altera (www.altera.com) are one of the many silicon companies announcing 42nm devices shipping in the next year or so. Xilinx fanboys - I'm sure they promise the same (picture an AMD/Intel bunfight if you will) - though I must confess I am friendly towards them as an ex employee of sorts, I am certain they are not the only ones proposing to produce devices at this process node in the near future. Intel and IBM being very much at the front of the curve, so to speak. The gap between theoretical limits being announced and actual manufacturing at the announced node seems to be getting a lot shorter. Is quantum really next, or is optical? As we get down to 32nm and beyond the so called 'moores law' (which seems only to really serve journalism as such ;) ) seems to really, genuinely be nearing the limits. What IS next after silicon transistors on a die? Gallium is supposedly running out (due to flat panels) and that's only a doping chemical for speed, still in the silicon domain, not a real sea change of technology. Whats going to happen to the size/power curve? Even multicore processors will suffer as long as they are still roadmapped out on the same substrate. Are we really running out of time now? I don't really hear of the 'next big thing' in any form other than conjecture at the moment..?

Re:Is the gap closing? (1, Interesting)

zappepcs (820751) | about 6 years ago | (#24165845)

IANA nanotechnology specialist, but IMO the 'next big thing' might be something like an i686 on the same die as a Xilinx whopping-big FPGA so that you can do hardware encryption at memory bus speeds or things like that. When the hardware gets smaller you can be more creative about how you combine it with other hardware.

Personally, I'm looking forward to the ARM-23 running ARMLinux on a PDA with realtime encryption and DSL sized wireless bandwidth. When you can jam a bunch of hardware in a tiny place, things like that become possible. So I opine that the next big things will be systems on die where hardware is combined with what is now considered ancillary hardware so that the Dick Tracy wristwatch tv will become a reality.

Sorry, not sure how this helps with flying cars, but I can see the Dick Tracy thing.

Re:Is the gap closing? (1)

Colourspace (563895) | about 6 years ago | (#24165869)

Should have left it at IANA....

Re:Is the gap closing? (1)

Colourspace (563895) | about 6 years ago | (#24165879)

Sorry, just having re read your post, y'know, just to make sure I'm not going mad... I should have marked it +5 hilarious.. If you are not clued up about the subject matter then please don't hit reply. Dick Tracey my ass, waste your keystrokes elsewhere luddite!

Re:Is the gap closing? (-1, Flamebait)

Anonymous Coward | about 6 years ago | (#24166757)

Someone call the wah-mbulance, We have a casualty!

Umm (0)

Anonymous Coward | about 6 years ago | (#24166255)

You mean like a Virtex II-Pro? [xilinx.com]

Re:Is the gap closing? (0)

Anonymous Coward | about 6 years ago | (#24168177)

FYI Xilinx already sells PPC cores (V2-Pro, V2-ProX, V4 FX/V5 FXT) onboard and I think Altera has ARM cores.

Re:Is the gap closing? (1)

LanceUppercut (766964) | about 6 years ago | (#24166135)

This is a direct consequence of your misunderstanding of Moore's Law, journalism or not. Moore's Law does not insist on miniaturisation, but rather on the degree of integration (DoI). Until the relatively recent time, the minuaturisation was the main factor in increasing the DOI. It is no longer. And that is not a problem. The current trend is the increase of the DoI derived from the increase of the absolute size of the chip. This is a well-established trend already, just look at the multi-core CPUs. So, in fact, the current "thing" is indeed "big" in the literal sense of the word.

This is what will sustain the Moore's DoI trend as long as necessary, until we finally find your "next big thing" in therms of miniaturisation technology. If ever.

Re:Is the gap closing? (1, Informative)

Anonymous Coward | about 6 years ago | (#24166183)

Both Xilinx and Altera are fabless so their time to market depends on their ability to execute given the process parameters or cell libraries supplied by the foundry of their choice.

Oh great... (1, Insightful)

Chordonblue (585047) | about 6 years ago | (#24166691)

All this so we can fit another 10 or 20 cores that programmers won't use... Or was that too bitter?

Re:Oh great... (1)

Skapare (16644) | about 6 years ago | (#24167217)

Eventually they will figure out to just put RAM there in place of the extra cores.

Re:Oh great... (1)

Mattsson (105422) | about 6 years ago | (#24174961)

Hmm... Wonder how much performance gain there would be with 2GB of RAM with L2 cache performance. =)

That would lead to a similar situation as with the Chip-RAM/Fast-RAM architecture used in the old Amiga architecture, where there's one area of RAM that the CPU has blazing fast access to and one where the CPU has as slow access as the other devices.

Re:Is the gap closing? (1)

Chemisor (97276) | about 6 years ago | (#24167075)

> What is next after silicon transistors on a die?

Next, you optimize your bloaty software. Word Perfect 5.1 ran just fine on an 8MHz 286, and had a capaibility set not too different from the current word processors. Any piece of software can be optimized to the point when most operations are instantaneous

Re:Is the gap closing? (1)

jfim (1167051) | about 6 years ago | (#24169809)

Next, you optimize your bloaty software. Word Perfect 5.1 ran just fine on an 8MHz 286, and had a capaibility set not too different from the current word processors.

And it still runs fine. Software doesn't rot(although media does) so you can still use it if you want to, especially considering the x86 architecture is quite backwards compatible.

Obviously, if the average computer gets faster and has more memory, programs will trade some optimization in order to have better code maintainability, more features, etc.

Any piece of software can be optimized to the point when most operations are instantaneous

I think this is very dependent on the type of software. I'm sure some people in the movie industry would love if 3D rendering would become instantaneous.

Re:Is the gap closing? (0)

Anonymous Coward | about 6 years ago | (#24168067)

I once heard germanium would allow smaller feature sizes?

Been there done that (5, Funny)

Anonymous Coward | about 6 years ago | (#24165789)

I've laid floating lines 1 nm apart with my boat in the past. 25 nm could be done if you wanted but that's getting pretty far apart. Who wants this grid, and why the heck would you use a laser to create light and dark zones every 200 nautical miles?

Re:Been there done that (1)

Yvan256 (722131) | about 6 years ago | (#24165863)

It's nanometers, you stupid Anonymous Cow....

Oh wait, I see what you did here.

Re:Been there done that (3, Funny)

rubycodez (864176) | about 6 years ago | (#24166271)

your story sounds fishy to me.

Re:Been there done that (1)

hostyle (773991) | about 6 years ago | (#24166769)

You should have seen the etching that got away! It was <- THIS BIG -> ...

Re:Been there done that (1)

ByteSlicer (735276) | about 6 years ago | (#24171335)

Who wants this grid, and why the heck would you use a laser

See, the grid is to keep the sharks in, and the laser has to be mounted on the shark's head...

What would be interesting is.... (0)

Anonymous Coward | about 6 years ago | (#24165807)

They kept the chips the same size, but imprinted smaller, thus getting like a 4 times more powerful chip, instead of having the same size of power in something that might snap in to when pressure is applied to it.

Re:What would be interesting is.... (2, Funny)

argent (18001) | about 6 years ago | (#24166615)

That's only a problem if you don't heat the queso before you dip the chips in it.

Shrinking in size is one part of the problem (3, Informative)

feranick (858651) | about 6 years ago | (#24165829)

The process of making smaller features is only a small fraction of the problem in producing 25nm (or smaller) Si-based electronics. Left aside quantum effects, which start to dominate at length scales smaller than 10nm, stability and electrical leakage through the gate are the most significant problems. When Intel went from 65nm to 45 nm, it wasn't just a "shrinking" process, but an all new use of materials design had to be used to deal with the gate current leakage. In simple words, the silicon oxide insulator was just too thin not to leak. The new metal high-K (Hafnium-based) is the major step that allowed those chip to be made. This research is good, but it solves only a small fraction of the difficulties the electronics industry faces in dealing with Moore's law.

Re:Shrinking in size is one part of the problem (2, Interesting)

LanceUppercut (766964) | about 6 years ago | (#24166051)

Exactly. And it is not only limited to the physical effects themselves, but also includes the limited capabilities of the modern design and verification software necessary to simulate these effects on any input of any pratical size in any practical time.

Designing these chips will be expensive. And that's exactly what Moore's Law is about. Not some stupid miniaturisation of the devices.

linewidth != wavelength (4, Informative)

tsjaikdus (940791) | about 6 years ago | (#24165873)

You can create much smaller lines than the wavelength of your light. You use tricks for that, but that's how it is done at Samsung, IBM, Intel, etc. for ages.

Moore's Law (2, Funny)

Yvan256 (722131) | about 6 years ago | (#24165895)

Everyone keeps mentioning Moore's Law and all the problems that go with it. Why isn't there anyone to stand up to him so that we're finally free of his damn limiting laws?

Oh wait, that kind of law. My bad.

Re:Moore's Law (1)

hostyle (773991) | about 6 years ago | (#24166785)

Is that the one that goes "Anything that can get smaller, will get smaller?"

Re:Moore's Law (0)

Anonymous Coward | about 6 years ago | (#24174851)

It's not a "law" at all, as he himself has said. It would be more accurately named "Moore's interesting trend." Also it predicts only a doubling of transistor count every 2 years, which isn't the same thing as doubling of speed (e.g. dual cores are nowhere near twice as fast as one for typical workloads.)

Is this useful? Try making transistors with it. (0)

Anonymous Coward | about 6 years ago | (#24165931)

A 25nm CPU implies that its transistors can have a 25nm channel length. From the article, it sounds like they can simply make parallel lines, not transistors.

Using this technique, would everything have to be separated by 175nm? This would still make an extremely fast transistor due to the smaller dimensions, but it would take up a large amount of space (usually less space implies faster due to smaller capacitances--hence more transistors per unit area is faster). Also, how would this work with a mask? All transistor channels would have to be aligned, and the mask would only block light perpendicular to the channels? That's not very nice.

As stated earlier, this is interesting because they etched a feature smaller than the wavelength of the light.

Moore's Law is not restricted to silicon (2, Insightful)

mschuyler (197441) | about 6 years ago | (#24165963)

Though Gordon Moore certainly developed his law around the silicon chip, the interesting thing about his law is that it is retroactive and not restricted to silicon, leading to the possibility that even if there is a real limit to silicon, something else will come along to replace it and keep the law going through another iteration. Whether that turns out to be holographic, 3-D, biological, or whatever is anyone's guess at this point.

If you start out with the Hollerith census counting machines developed for the 1890 census (the ones that used cards the size of dollar bills because they had a bunch of dollar bill boxes, hench the size of the punched card and the 80-column screen), then move to electric relay switches, then to vacuum tubes, then to transistors, then to silicon, the whole thing is an exponential curve with a doubling every 18-24 months.

Every time I hear someone saying, "We're eaching the end of Moore's Law," I think: Not.

Re:Moore's Law is not restricted to silicon (2, Insightful)

ucblockhead (63650) | about 6 years ago | (#24166687)

It will end. It is just a question of when.

Re:Moore's Law is not restricted to silicon (0)

Anonymous Coward | about 6 years ago | (#24166987)

Though Gordon Moore certainly developed his law around the silicon chip, the interesting thing about his law is that it is retroactive and not restricted to silicon, leading to the possibility that even if there is a real limit to silicon, something else will come along to replace it and keep the law going through another iteration. Whether that turns out to be holographic, 3-D, biological, or whatever is anyone's guess at this point.

If you start out with the Hollerith census counting machines developed for the 1890 census (the ones that used cards the size of dollar bills because they had a bunch of dollar bill boxes, hench the size of the punched card and the 80-column screen), then move to electric relay switches, then to vacuum tubes, then to transistors, then to silicon, the whole thing is an exponential curve with a doubling every 18-24 months.

Every time I hear someone saying, "We're eaching the end of Moore's Law," I think: Not.

Moore's Law was never meant to be endless and there are several factors that will end it. Cost is the likely ender since there's a cost doubling that goes along with it. There's also physics barriers. Yes I know nano computing will extend it but for how long? Ultimately even if we can keep rationalizing the cost we will hit practical if not physical limits. Moore's Law is often mistaken for constant law of nature like Conservation of Energy. It was meant to predict a pace of progression. It's like population. If we kept reproducing at our current rate the biomass of humans would reach the Moon in a shockingly short amount of time. Resources and physical limitations will stop that from happening. The same will happen with Moore's Law. Does it mean Moore was wrong? No absolutely not it just means outside factors will eventually hault the progress.

paves the way? (0)

Anonymous Coward | about 6 years ago | (#24165977)

More like etches the way for 25nm CPUs

Re:paves the way? (1)

hostyle (773991) | about 6 years ago | (#24166801)

You mean soon we'll have etches all the way down?

Re:paves the way? (1)

Skapare (16644) | about 6 years ago | (#24167245)

I guess someone just wanted to have the world's smallest Etch-A-Sketch [wikipedia.org] .

Anoter fake Moore's Law (1)

LanceUppercut (766964) | about 6 years ago | (#24166025)

Moore's Law is not in any way tied to miniaturisation of chip features, as the clueless ones seem to believe.

Misleading title (0, Offtopic)

Igasagu (953986) | about 6 years ago | (#24166035)

I'm still waiting for CPUs that are 25nm, as in the whole chip itself is 25nm.

This doesn't impress me at all (5, Informative)

Cutie Pi (588366) | about 6 years ago | (#24166157)

First, IAALE (I am a lithography engineer) working on Intel's 22nm process technology. Let's clear up a few misconceptions:

1) The name of a logic node is directly related to the size of the features being made. Those names (e.g. 65nm, 45m, 32nm, etc.) used to relate to the "half-pitch" of the minimum pitch that was printed. But that is not true today. 65nm used a minimum pitch of ~200nm, 45nm used ~140nm and 32nm is using ~100nm. The next node, 22nm is slated to use minimum a pitch of 72nm. The features discussed in this article have a pitch of 50nm, which would be equivalent to the node after 22nm, i.e. 16nm.

2) It's not hard to print features smaller than the wavelength of light. For the lens based systems we used, the Rayleigh criterion gives the minimum pitch possible: 0.25*lambda/NA, where lambda=wavelength (193nm) and NA=numerical aperature (1.35 for the best lenses). So 72nm is the minimum pitch, already much smaller than the wavelength

3) I hate to break it to these researchers, but interferometry has been used for a looong time to make gratings. Search for "interferomety lithography" on Google Scholar. The fourth link is called "Nanolithography using extreme ultraviolet lithography interferometry: 19 nm lines and spaces". That paper is from 1999. And they did that one exposure, not three (using a smaller wavelength).
You would actually need at least one more exposure to divide the grating into something that resembled a logic circuit. The technique in this artcle is not practcal for a number of reasons, but we can do better than them using pitch-doubling techniques and only two exposures.

Re:This doesn't impress me at all (3, Funny)

hal9035 (827327) | about 6 years ago | (#24168115)

so, in conclusion, return the grant money, all of it.

A size perspective (4, Interesting)

Skapare (16644) | about 6 years ago | (#24167173)

Here is a perspective on the size of these 25nm stripes and grooves. If a cross-hatch of these stripes and grooves done both vertically and horizontally each had a pixel of a picture placed on it, then the number of high definition 1920x1080 pictures you could fit in just one square millimeter would be 20.833 pictures wide by 37.037 pictures high, for an average of 771.605 pictures per square millimeter ... a half minute of video at 25 fps. For the metric challenged, that's 529.166 pictures wide by 940.741 pictures high, for an average of 497808.642 pictures per square inch ... over 4.6 hours of video at 30 fps.

Re:A size perspective (0)

Anonymous Coward | about 6 years ago | (#24169691)

Sure, it's small.. but so are the atoms in my body.
 
Considering that it'll take over 30 bytes, or over 200 bits (which will each take like 7 transistors).... it doesn't seem too fair to relate the size of the grating to a certain number of images.

Re:A size perspective (1)

MilesAttacca (1016569) | about 6 years ago | (#24174013)

Yes, but how many Libraries of Congress can you fit in there?

Re:A size perspective (1)

Mattsson (105422) | about 6 years ago | (#24175025)

I thought the commonly used unit was Library of Congress. =/
How many pictures are there per LOC, so that I can do a conversion?

Re:A size perspective (1)

Xyde (415798) | about 6 years ago | (#24181547)

I don't understand, can you please use a car analogy?

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