Welcome to the Slashdot Beta site -- learn more here. Use the link in the footer or click here to return to the Classic version of Slashdot.

Thank you!

Before you choose to head back to the Classic look of the site, we'd appreciate it if you share your thoughts on the Beta; your feedback is what drives our ongoing development.

Beta is different and we value you taking the time to try it out. Please take a look at the changes we've made in Beta and  learn more about it. Thanks for reading, and for making the site better!

VHDL or Verilog For Learning FPGAs?

timothy posted more than 5 years ago | from the which-has-the-better-swag dept.

Education 301

FlyByPC writes "We're in the first stages of designing a course in programmable devices at the university where I work. The course will most likely be centered around various small projects implemented on an FPGA dev board, using a Xilinx Spartan3-series FPGA. I have a bit of experience working with technologies from 7400-series chips (designing using schematics) to 8-bit microcontrollers to C/C++. FPGAs, though, are new to me (although they look very interesting.) If you were an undergraduate student studying programmable devices (specifically, FPGAs), would you prefer the course be centered on VHDL, Verilog, a little of both, or something else entirely? (...Or is this an eternal, undecidable holy-war question along the lines of ATI/nVidia, AMD/Intel, Coke/Pepsi, etc...?) At this point, I've only seen a little of both languages, so I have no real preference. Any input, especially if you're using one or both in the field, would be very helpful. Thanks, and may all of your K-maps be glitch-free."

Sorry! There are no comments related to the filter you selected.

Where are you located? (5, Interesting)

hpa (7948) | more than 5 years ago | (#28159869)

Personally, I would say that Verilog is more C-like: weakly typed, compact, efficient notation, whereas VHDL is much more Ada-like: strongly typed, often verbose, but can catch errors that the other one can't.

In industry, as far as I can tell, Verilog seems to be more used in North America and VHDL in Europe, so that might affect what you care about, too.

Personally, I prefer Verilog.

Re:Where are you located? (0)

Anonymous Coward | more than 5 years ago | (#28159925)

In my courses the intro class used the schematic entry at first and then a brief exposure to both verilog and VHDL. The follow up course to it was done in VHDL. A lot of weird and 'unexpected behavior' will be seen and some students will spend hours trying to figure out what is wrong. My vote would be for VHDL because of this.

Re:Where are you located? (0)

Anonymous Coward | more than 5 years ago | (#28159945)

Military uses (and created) VHDL in America.

Or, rather, the DoD created VHDL way back when, so all stuff done with the military/defense department/gubment is done in VHDL.

But yes, the US private sector generally uses Verilog. (Other N. American countries, I can't say)

Re:Where are you located? (5, Interesting)

phulshof (204513) | more than 5 years ago | (#28159981)

I agree with the above post, though I personally prefer VHDL. That might however have something to do with me having designed ASIC/FPGAs for about 11 years now using VHDL though. :) Both are very powerful languages these days, and I see no problem in teaching a course using both languages, showing how to create the same hardware using different language constructs.

Re:Where are you located? (-1, Redundant)

Anonymous Coward | more than 5 years ago | (#28160045)

Personally, I would say that Verilog is more C-like: weakly typed, compact, efficient notation, whereas VHDL is much more Ada-like: strongly typed, often verbose, but can catch errors that the other one can't.

In industry, as far as I can tell, Verilog seems to be more used in North America and VHDL in Europe, so that might affect what you care about, too.

Personally, I prefer VHDL.

Re:Where are you located? (5, Insightful)

Man On Pink Corner (1089867) | more than 5 years ago | (#28160131)

Speaking as someone who just got his first Verilog-based design working on a Nexys2 board, I can confidently say that there are two serious mistakes a n00b can make:

1) Thinking of Verilog (or any HDL) as anything like C. Yes, there are semicolons. Yes, you can write a "for" loop, if you want to synthesize a huge mess. That's about it.

2) Thinking of Verilog as a programming language at all. HDL stands for "Hardware description language," and that's what they are.

Verilog is fun stuff, but it's the hardest thing I've ever taught myself. For those who are trying, I've found the Bhasker books on synthesis to be quite useful, Pong Chu's FPGA Prototyping with Verilog Examples to be reasonably useful, and most of the others to be fairly worthless. Too many books focus on simulation at the expense of synthesis practices, IMO.

Also have just received Richard Haskell's new books [] on basic and advanced Verilog using the Basys and Nexys2 platforms. They look very good at first glance but I haven't yet had a lot of time to spend with either of them.

Re:Where are you located? (1)

linzeal (197905) | more than 5 years ago | (#28160221)

Agreed, too may people jump from C++ or Java directly to HDL without a good electronics or assembly course inbetween. I would suggest you take both before you jump in with HDL.

Re:Where are you located? (1)

KDR_11k (778916) | more than 5 years ago | (#28160699)

Dunno, I didn't have any trouble with learning Verilog despite never having seen Assembly language before and lacking understanding of electronics (I know some basic stuff but could never get the calculations right) though I did have experience with writing logic for videogames (especially the Total Annihilation COB format which often runs frame based and multithreaded). I found the massive parallelism easy to visualize.

Re:Where are you located? (1)

Mike1024 (184871) | more than 5 years ago | (#28160161)

In industry, as far as I can tell, Verilog seems to be more used in North America and VHDL in Europe, so that might affect what you care about, too.

When I worked at (UK-based processor designers) ARM [] , Verilog was the language of choice. I've been told VHDL is popular in academia, while Verilog is more popular in industry.

That said, the underlying concepts are pretty similar, and those are what you're teaching really, so either choice would be reasonable.

Re:Where are you located? (2, Interesting)

SydShamino (547793) | more than 5 years ago | (#28160515)

Verilog is more popular in the ASIC design industry, for certain. But I work at a large test instrument manufacturer whose products are based heavily on FGPA design, and we are exclusively a VHDL shop.

It is my understanding that Verilog is moving towards stricter type definitions, so that it can get some of the benefits that entails. If you, the submitter, are looking to learn/teach a language least likely to change in the near term, go with VHDL.

That said, a good engineer should be able to sit down with the unfamiliar language and read it, and after a week training course write in it with professional quality. So whichever you teach, your good students will do fine in their careers.

Re:Where are you located? (1)

arktemplar (1060050) | more than 5 years ago | (#28160327)

Yes, essentially I'd agree with you.

However the thing is this, it's easier to get synthesiseable code in verilog that will correspond to your code directly, if you have experience, that is. However, VHDL seems to be better in my opinion only because it is more structured.

Ok - so the thing is, I've done significant work in both. I kind of liked the fact that VHDL was more structured and readable, however Verilog seems to have more support. Now, apart from this the differences, are mostly in getting synthesiseable results from your code, it's easier to get code match the RTL, like I've already said, if you're working in Verilog, plus synthesisers also have better support for Verilog. However, after getting started on verilog, VHDL is much more attractive in my opinion.

Re:Where are you located? (1)

kestasjk (933987) | more than 5 years ago | (#28160377)

I had a brief experience with Xilinx during a computer science course. It was (no exaggeration) the most buggy, error/crash-prone Windows 95 throwback nightmare piece of software I've ever used. Everyone in the labs were often unable to complete (simple hardware fundamentals 101) assignments, just because of software problems.

YMMV of course, but if I never have to use Xilinx again I'll be glad.

Re:Where are you located? (1)

SydShamino (547793) | more than 5 years ago | (#28160567)

The biggest problem with Xilinx' compilation software at the moment is their timing analysis. The industry is moving towards system models for timing analysis, based around Synopsys Design Constraints. Their use in ASICs is already pretty common, but for FPGA design their use is pretty new.

Altera's TimeQuest analyzer in their Quartus II software is SDC-based, so learning that gets you the latest and greatest in terms of analysis capabilities. Xilinx still uses classical, chip-centric timing analysis software. I would expect an SDC-based model from them in the near future, but if you learn with what they currently offer, you'll need to learn again.

That said, you'll have success with either company at this point. The Altera Max+Plus II software I was forced to use in college was some of the buggiest, least-intuitive, poorest quality software I've ever seen. But the latest versions of Quartus II are good enough to be better than most third-party tools for synthesis, and perfectly functional for place and route and analysis.

Re:Where are you located? (2, Interesting)

drmerope (771119) | more than 5 years ago | (#28160385)

I agree about the industry part, although I find it ironic since VHDL arose from DARPA funded work whereas Verilog is a proprietary innovation turned international standard. At school I learned VHDL though. This wasn't a problem when it came time to use Verilog at work.

My advice: cut against trend. If you're a North American school, use VHDL. If you're in Europe, use Verilog. It may be the only chance for your students to taste the other side.

The insanity of VHDL is attaching two things that you know are 'just wires'. In my experience you spend quite a lot of time writing type-conversion adapters.

C-to-Verilog dot com (0)

Anonymous Coward | more than 5 years ago | (#28160573)


Another possible solution is to use automated translation between C to VHDL or Verilog. The website is an open source project which gives you a compiler and an on-line service for compiling C to Verilog.

Re:Where are you located? (1)

jcasper (972898) | more than 5 years ago | (#28160611)

The quote I've always heard (not sure where it came from): "VHDL was created by hardware engineers who know nothing about programming languages. Verilog was created by computer scientists who know nothing about hardware."

In practice I've had to deal with both on a regular basis, including single designs with both VHDL and Verilog modules. I'd say teach digital design and let them learn whatever language they want to implement what they learn in class; Xilinx tools can handle both seamlessly, why not let them choose? Show examples from both in the slides.

Re:Where are you located? (0)

Anonymous Coward | more than 5 years ago | (#28160725)

In industry, as far as I can tell, Verilog seems to be more used in North America and VHDL in Europe, so that might affect what you care about, too.

I'll second this. The courses I took in school (Georgia Tech) did everything in VHDL. Some of those I knew who went on to work in the field remarked that they wished we had learned Verilog instead, as it's much more common in industry. The impression I always got was that "Verilog vs. VHDL" is somewhat like "C vs. Pascal" used to be - the former is used a lot more in real applications, and allows more "bare metal" access, while the latter is a better teaching/modeling tool, and gets used more in academia. Which one you choose, then, should probably be based on whether your focus is mainly to train people for jobs in which they'll use a HDL, or teach them the concepts involved. Sort of like (to make another flawed analogy) IT vs. Computer Science.

Re:Where are you located? (1)

Austerity Empowers (669817) | more than 5 years ago | (#28160727)

A lot of people compare Verilog to C, and VHDL to Pascal (ADA lite?). Either way I find that a) you will need to know both, if you are going to be in this business, b) Companies that enforce A language, in the US, enforce Verilog, companies that leave it to teams, use either VHDL or Verilog. So if you had to choose just one, and you live in the US, I say choose Verilog ;) That said, the first ASIC I did was in VHDL (which I learned in school). I continued that in single-person FPGAs which I wrote, without objection. In my present company I was forced to learn Verilog, and I can't say that I long to go back to VHDL or have "been converted".

Both languages are designed to simulate, not synthesize. As such, the language ultimately is just the tool, "thinking hardware" in terms of the synthesizeable subsets of the languages and the realization of hardware the tools come up with is identical in both languages. The constructs that produce a given hardware are generally very parallel (in fact there's a book out there, I forget the name, that puts VHDL right next to Verilog for a given construct). Neither language is especially more compact or "R.A.D." than the other. VHDL expect to spend more time fighting your compiler and subjugating the strongly-typed aspect. Verilog expect to spend more time debugging subtle and unexpected results of improper use of the language (like C, it will do what you ask, but not always what you meant!).

I've found that Icarus is a great free Verilog simulator for Linux, and I love it, so that's a good budget choice. In general though, consider your simulation tools as the driving force in your choices. Some professional tools are better at VHDL or better at Verilog (which has a number of "versions", adding very nice features that aren't always available in a given sim). Some run far faster with one language or another. In the long run this will all balance out, but we've been saying that for a decade and there are still (increasingly small) imbalances. Examine your simulation/verification model, identify which features you may want (things like "do I want to use a large randomly accessed text file for input vectors?") and see which language offers the most robust support with your tool, and if it requires proprietary language extensions to make that happen (very common with verilog).

Most synthesizers take both and work pretty much equally with either language.

Re:Where are you located? (5, Insightful)

SydShamino (547793) | more than 5 years ago | (#28160801)

Having now read through the entirety of the comments on this story, the trend I see is that:
A) students who learned with VHDL then went on to a career with Verilog think the transition was easy and either language is fine, while
B) students who learned with Verilog then went on to a career with VHDL, while rarer, think VHDL is a harder language, and
C) students who were forced to take VHDL when it wasn't in their career plan hated it, because it was so different than a programming language.

Based on that review, I'd say teach your students VHDL. The students that learn it and do well in your course will have the easiest time in the industry, and those that hate it probably won't become good HDL designers regardless.

Re:Where are you located? (1)

Rufus211 (221883) | more than 5 years ago | (#28160863)

It's not only where you are, but what part of the industry. From my experience most of the industry (Intel, AMD/ATI, Nvidia, etc) are all Verilog houses. On the other hand anything that interacts with the government (research labs, IBM, defense contractors) are VHDL houses.

But really, it doesn't matter in the long run since there are no fundamental differences between the two. The syntax will take you a month or so to get used to, but the hardware you're designing will be the same. The hard part of hardware design is not typing out the code, but creating a good micro-architectural design with good documentation and diagrams of how all the pieces connect together. Once you have a solid uarch, translating that into either Verilog or VHDL should be very straightforward.

You forgot (2, Funny)

OAB_X (818333) | more than 5 years ago | (#28159879)

You forgot a few:

Linux vs. *BSD
Gnome vs KDE


Re:You forgot (0)

Anonymous Coward | more than 5 years ago | (#28160169)

Nikon vs. Canon
Republican vs. Democrat
Ford vs. GM

Re:You forgot (2, Funny)

XPeter (1429763) | more than 5 years ago | (#28160201)

Ford vs. GM eh?

No competition here, they'll both be going into bankruptcy soon.

Re:You forgot (1)

SydShamino (547793) | more than 5 years ago | (#28160615)

Ford is in pretty good shape, not because of their truck divisions but because they didn't abandon cars entirely and join their competition in a round of "Americans! Ugrg Ugrg big trucks low mileage screw quality!". While I have only briefly driven them, I understand that the Ford Focus is a rather popular, higher-quality vehicle for its price range. Cars like that saved them more than anything else.

Re:You forgot (-1, Troll)

XPeter (1429763) | more than 5 years ago | (#28160175)

VI and EMACS are two completely different things.

VI is like BSD. Nobody uses it or gives a flying fuck about it.

EMACS on the other hand is a very useful text editor.


Re:You forgot (1)

SydShamino (547793) | more than 5 years ago | (#28160589)

?? What you state makes no sense. I use VI as my text editor and EMACS as my operating system.

Re:You forgot (1)

vrmlguy (120854) | more than 5 years ago | (#28160183)

You forgot a few:

Linux vs. *BSD
Gnome vs KDE


It's emacs vs vi, you insensitive clod!

Re:You forgot (3, Funny)

tommituura (1346233) | more than 5 years ago | (#28160359)

You forgot a few:

[--]VI vs. EMACS [--]


No, he didn't forget that. You see, he wrote:

(...Or is this an eternal, undecidable holy-war question along the lines of ATI/nVidia, AMD/Intel, Coke/Pepsi, etc...?)

... and it's quite clear that VI is the winner.

Re:You forgot (1)

RoFLKOPTr (1294290) | more than 5 years ago | (#28160577)

You forgot a few:

Linux vs. *BSD VI vs. EMACS Gnome vs KDE


Well Gnome and KDE both suck, so that argument is irrelevant.

Schmatic layout? (2, Interesting)

Sillygates (967271) | more than 5 years ago | (#28159881)

I'm in Computer Science, a somewhat related field, and I've had to take a few hardware courses during my time in school.

I felt like Xilinx Schematic layout was a great first step, because it introduced the circuit theory in a visual way.

Re:Schmatic layout? (1)

samirbenabid (1223166) | more than 5 years ago | (#28159897)

I second that.

Re:Schmatic layout? (1)

amigabill (146897) | more than 5 years ago | (#28160133)

That's a good point, but many students will have already been exposed to schematics in earlier prerequisite courses before being tossed into an FPGA class. In the real word today, people are using vhdl and/or verilog and or other languages isntead of schematics for FPGA work. Look at those FPGAs today, holding millions of gates to use, it'd be unreasonable to design for that using schematics. Look at available resources like which have open-source projects/cores in vhdl and in verilog. In the real world, the simulators most in use today are verilog and/or vhdl and/or other languages.

I think it'd be nice to have some exposure for your students in what is done in real life as well as whatever benefit there is to starting with schematic. Perhaps this FPGA course could be a follow up to a more basic digital logic design course showing schematics etc. as a prerequisite?

Re:Schmatic layout? (0)

Anonymous Coward | more than 5 years ago | (#28160319)

I am a Computer Science student who took a similar course to what you are describing. We learned on the Xilinx program too and I have to say that learning how to use the Xilinx Schematic program before learning how to program in Verilog/VHDL was a great deal of help as it allowed us to understand how to read the diagnostics. That said, I learned VHDL and felt that it was almost identical to Verilog in the scope of the class that I am in, I imagine that there will be major differences in the future however, at the introductory phase, I would not worry about it.

Re:Schmatic layout? (0)

Anonymous Coward | more than 5 years ago | (#28160151)

I agree with this. I started with VHDL, discovered the hard way that most of the language is aimed at modelling and simulation, not physical FPGA programming, and started again with schematic capture. Once I got up to speed with schematic capture, it became obvious which parts of VHDL were actually usable for FPGA programming, and which were only useful for generating simulated test inputs and responses. The problem with VHDL and Verilog is that they look like really general programming languages, and indeed they can be used that way for simulation and modelling, which is what they were originally designed for. However for FPGA programming, only a small subset of these languages can be used, and until you understand how the compiler converts that subset into gates, then using them is a very frustrating experience. Once you understand the limitations of VHDL in actually programming FPGAs, the combination of this and schematic capture with VHDL testing code in a simulator is very powerful. So VHDL or Verilog are essential tools, but I would recommend starting with schematic capture, and then go on to explaining how to implement that layout in VHDL/Verilog, and only describe the higher level parts of the languages when you come to writing simulated code to generate test inputs in a simulator.

Re:Schmatic layout? (1, Insightful)

Anonymous Coward | more than 5 years ago | (#28160357)

Absolutely not. If you want more than just sample logic circuits, schematics are a dead-end.

In my second university year (Electronics Engineering), I chose a semester-long microprocessor design project. They showed us how to make it using schematic, and everybody did it like that. I found it to be a debugging nightmare. Up until one day before the deadline, I couldn't find the bug in the implementation of a particular opcode (It took me about 2 weeks to design & enter the schematic and 4 weeks debugging and fixing things).

That's when I gave up, dumped the whole schematic, started learning Verilog from examples and capturing my design using Verilog instead of schematic. I finished it in more or less 8 hours (and I even slept that night).

As about Verilog vs VHDL, all I can do is send in this link:

Re:Schmatic layout? (2, Insightful)

SydShamino (547793) | more than 5 years ago | (#28160631)

No one is doing schematic design for FPGAs any more. If you want to teach schematic design, get a schematic capture and layout package and teach PCB design. There are plenty of things to learn at the board-design level, too, and you can teach some of your circuit theory that way if you wish.

don't focus on the language (3, Insightful)

downix (84795) | more than 5 years ago | (#28159895)

First mistake I always find in these courses is to focus on the language, and not on the skills necesary to make full use of them. I would actually focus the course on your existing schematic and know-how, and bring in the languages used later on, preferably both presented alongside such as SystemC. But that know-how will be far more valuable than any single language possibly can be.

Re:don't focus on the language (1)

vlm (69642) | more than 5 years ago | (#28160395)

Absolutely seconded. If you understand:

Interfacing hardware (so the labs can control real world stuff, even if only a LED),
Logic including all kinds of flipflops,
race conditions (folks whom started programing on CPUs always have trouble adjusting to this),
fork/join (and whatever the VHDL equivalent is),
initial vs always (initial as a type of always that only runs once or whatever),
parallel "programming" in general,
computer or other system interfacing,

then, and only then, you're all set to do both Verilog or VHDL. Even if you can only do one or the other in lab, try to at least gloss over both at lecture time.

Designing a class by starting with the specific lab tool is kind of like designing a literature class beginning with word processor font selection.

If you don't know the theory, you're lost lost lost no matter if you choose Verilog or VHDL.

VHDL of course (4, Interesting)

wiredlogic (135348) | more than 5 years ago | (#28159903)

Let's put it this way. I once implemented a subset of TCL in pure VHDL to implement feature rich scripting for simulation data. That can't be done in Verilog without dropping out to C.

Re:VHDL of course (0)

Anonymous Coward | more than 5 years ago | (#28159923)


Re:VHDL of course (1)

scatterbrained (144748) | more than 5 years ago | (#28160285)

Sounds like an argument against VHDL to me... Verilog PLI (programming language interface) was for years one of the things that made verilog better than VHDL. (And it's not just C, there are PLI bindings for scripting languages, too). Not to mention using a simulator like ModelSim you can write Tcl code to interact with the simulation without resorting to tricks like this.

Re:VHDL of course (0)

Anonymous Coward | more than 5 years ago | (#28160895)

Forget the PLI unless you really need the full power of a software language. SystemVerilog gives you classes with some basic inheritance, among other things. Companies using verilog are definitely going in that direction.

Learn Both (2, Insightful)

cthulhuology (746986) | more than 5 years ago | (#28159905)

Seriously, learn both. The languages aren't that far apart in reality. VHDL is simply a little more verbose. Both can be learned to an extent that you can make sense of most of the designs on in a day. (Yes I said a day! At least that is how long it took me.) There's really no good reason to avoid the little bit of work, that will make your life easier in the long run. If you really want to learn to program FPGAs you need to learn to read other people's designs. Many of the things you won't just figure out playing around with FPGAs have been solved by other people who have kindly placed designs under open licenses. However, since you have no idea which design language it will be, it is better to become familiar with both the popular ones. Eventually, you'll inevitably choose one for your own projects, and the only way to adequately assess them is to use both for a while and figure out which one meets your needs and you can tolerate.

Re:Learn Both (1)

JewFish (315210) | more than 5 years ago | (#28160025)

Did you mean

Re:Learn Both (1)

OeLeWaPpErKe (412765) | more than 5 years ago | (#28160035)

Opencodes ? You mean [] ?

Verilog, at least where I work (3, Informative)

amigabill (146897) | more than 5 years ago | (#28159929)

I work at a chip company doing ASIC and custom SOC microprocessor stuff. We mostly use verilog here for our stuff. Most of the VHDL I see comes from customers, which often gets blended into our verilog platforms. All our RTL IP cores are verilog that I know of, at least that I've used/seen, and our integration work to make platforms out of all the IP pieces is verilog. What we synthesize to gates is also a verilog gates netlist result that goes to place/route into silicon.

In college the class I took that involved this sort of thing was in VHDL, and I hated that. had me really nto wanting to do this kind of work, I was really happy when I was exposed to verilog and I didn't hate it, and I've been a chip guy for over 10 years now.

But as I understand, VHDL is far more popular in some locations, and verilog in others, so jobs in other locales may be completely opposite to my work environment. It would probably be nice to show some of each to be a little familiar with both such as comparing/contrasting = to = and == to ===, but focus on one or the other for people to really get experience fitting pieces together and learning the general stuff about RTL design, etc. that are not as dependent on what language you use.

Re:Verilog, at least where I work (1)

amigabill (146897) | more than 5 years ago | (#28160007)

I meant comparing = to <= up there. Sorry, html ate my less than char

Another thought (1)

amigabill (146897) | more than 5 years ago | (#28160081)

Who's teaching the course, you? Have a look at them and see if you have a strong preference. Most people do one way or the other. I like Verilog and hate VHDL. I think the instructor should teach what he's more comfortable himself, so you're all more confident that he's teaching it correctly and not tossing out things that are confusing and may be somehow inaccurate in that language he's not as good with. I could help someone understand Verilog, but I would be a horrible teacher/mentor/tutor in VHDL trying to read and understand my answers to questions from the same (and/or other) books the students have. Other people are likely the reverse. Which way does this intructor for your course go? It'd be nice to find that out before you choose the wrong language for him.

Of course a superb instructor would be fluent in both, and more, but it'd be nice to avoid focusing on a good but fluent in only one teacher's weaker language.

Just pick one (1)

91degrees (207121) | more than 5 years ago | (#28159947)

Once you understand the concepts, switching to the other is relatively easy.

Verilog in Silicon Valley (2, Informative)

Bill of Death (777643) | more than 5 years ago | (#28159987)

I've worked at several top chip companies in Silicon Valley, in graphics and telecom industries, and they're 100% Verilog. I also suggest learning System Verilog as well, especially for testbench development.

Learn Both, and add System Verilog to the list. (2, Insightful)

gwait (179005) | more than 5 years ago | (#28159989)

Learn both, but start with Verilog. Many of VHDL's features are a bit academic, but once you know what is relevant from Verilog it makes it easier to find the "usable subset" of VHDL that's actually good for FPGA design.

System Verilog is the new kid on the block - they ironed out some of Verilog's oddities and added in some of VHDL's very useful features.
Altera already offer System Verilog support, Xilinx support is apparently on the way.

Verilog is a lot easier to learn in general, but VHDL has a great feature ("Records") which are akin to "structures" in C that Verilog doesn't offer.
System Verilog does, which is why it's on my list to learn next.

One other poster made a good point - learn logic design first, then make the language describe the logic for you.

If you don't have a clear idea in your mind how to map out a design in gates and flipflops, (block diagram on a whiteboard is always good) then you should not start coding in an HDL..
Both languages can lead you down the path of unsynthesizable nonsense that seems to simulate ok..

VHDL (1, Funny)

Anonymous Coward | more than 5 years ago | (#28159991)

Very Hard Dumb Language

Verilog all the way (0)

Anonymous Coward | more than 5 years ago | (#28160009)

It's much quicker to get things done in Verilog than VHDL. You need to know Verilog if you want to deal with post-synthesis/layout netlists anyway.

Also, SystemVerilog is where the future is, so much better to start with Verilog than VHDL.

Clearly VHDL (1)

HBSorensen (213613) | more than 5 years ago | (#28160019)

I hold a Bachelor of Science in Electronics Engineering and did quite a few projects on Xilinx FPGAs the last couple of which I did in VHDL. Love the language. Easy understandable and using the Xilinx Developer Software ( incl. Schematic tools ) development was a breeze. :-D Also did VHDL in the industry.

Verilog - Hands down (1)

Bearington (1555677) | more than 5 years ago | (#28160029)

My University used VHDL for our FPGA class because that was what the professor was familiar with. However, I found that around 75% of the reference material that I was able to find on the internet was written in Verilog. It would have been much easier if I had been writing verilog.

Re:Verilog - Hands down (1, Insightful)

Anonymous Coward | more than 5 years ago | (#28160331)

My undergraduate also taught us VHDL on Xilinx FPGAs. I haven't written a line of VHDL in 5 years, whereas I've done 4 internships (AMD & ARM) which all required Verilog knowledge and TAed a senior-level FPGA course (in Verilog) for the last 2 years. As far as the majority of industry goes, teaching Verilog will be of more use to your students (in addition to being much less verbose - the scale of their projects likely does not require much of VHDLs additional functionality). Also in the last few years (Verilog-2001), Verilog has addressed many of the shortcomings it had against VHDL. Automatic sensitivity lists, named ports, generate statements, etc.

In TAing this course, I've found Xilinx tends to prefer VHDL (some of their reference documentation and functionality of EDK requires some VHDL knowledge). I believe internally they are a VHDL house. Though this is a mild annoyance (one you many never encounter), I've found students do fine in using their toolchain with verilog.

Both Suck (1)

shinsplints (927720) | more than 5 years ago | (#28160057)

Both languages are old and the tools you have to deal with are incredibly complicated. I really don't think it will matter which you pick (I personally see Verilog used more in universities, but that doesn't make it the right choice). What you do need to worry about is coding style. Most students learning an HDL for the first time will come in with programming experience. They're going to try to use programming constructs and loops that, while appropriate for normal code will not represent synthesizable hardware. With that in mind you need to pound style rules into their heads. Since one of primary functions of each language is simulation (as opposed to synthesis) using legal code may lead you into trouble. Get around this by enforcing strict style rules. Example set of Verilog rules: [] [ copied from C. E. Cummings, âNonblocking Assignments in Verilog Synthesis, Coding Styles That Kill,â SNUG 2000. ( NBA.pdf)) Every time you code remind yourself "I am writing hardware".

Neither are very productive languages (0)

Anonymous Coward | more than 5 years ago | (#28160063)

Both are like using assembler. Useful for educational purposes, but someone using a higher-level language will have a productivy advantage. Look at CDL Cyclicity for a higher-level example (on source forge). It compiles down to verilog.

VHDL (0)

Anonymous Coward | more than 5 years ago | (#28160095)

I have taught both for use with Altera FPGAs. IMHO VHDL is better for teaching our students. The main problem we have here is that most of the students have already had lots of experience programming C++, java, pascal... One would think this is an advantage, however most of the students then program hardware like they would a software program. This just does not work. VHDL, is a strong typed language, and there are well defined sequential and current statements that fit well with hardware. Its not perfect, but I think it allows the students to differentiate a software and hardware program better. Lastly, from my experience, if you know one hardware language, it is not too difficult to pick up the other.

We use Verilog, and I recommend it. (1)

Shickdawg (205643) | more than 5 years ago | (#28160099)

At the university I teach at (Michigan Tech), we have selected Verilog design for our Altera FPGAs, and have been using it for 5+ years. I used Verilog in private industry before I started teaching and it *seemed* to be more common at that time. When I did some time at IBM back around 1998, they were using VHDL. One of the companies that hires a lot of our grads uses VHDL, and I keep having to tell students, "Look, if you know Verilog, all you need to get a handle on is the syntax of VHDL. Tell them that!"

Knowing both, I find students struggle enough with the concepts of logic design and simulation when they have a familiar kind of syntax (the C-based syntax of Verilog), let alone adding the complexity of VHDL's strange ADA-based syntax. I suggest Verilog.

Re:We use Verilog, and I recommend it. (1)

SydShamino (547793) | more than 5 years ago | (#28160717)

I work for a company that might be the VHDL-user you mention. I think students who learned VHDL produce code closer to production quality sooner, but it's not very different as you state. Verilog students just need more time to get used to the increased structure requirements of VHDL. I don't ask questions that require either during interviews - the underlying logic of system design is far more important.

If Verilog is moving towards stricter types as I've heard it to be, this difference will close up soon.

(Note that I learned neither in college but was hired based on that underlying logic basis. My HDL education started with a course offered by my employer. It now represents some 80% of my daily work.)

View from an undergrad (2, Insightful)

RabidTimmy (1415817) | more than 5 years ago | (#28160105)

I'd say I'm right about in the position you're talking about. I'm getting close to finishing my degree and a lot of the work I've done has been with FPGA's. My introductory class to the area used verilog (although no procedural, code for flip flops was given to us to instantiate). The next course we used VHDL and have used VHDL extensively since then. Both VHDL and Verilog have there strength and weaknesses but overall, for anything an undergrad will be doing, there are no significant difference in functionality. The only real difference I could see coming into play here is which would be easier to pickup. Verilog has a syntax similar to C. Operators are the same, variable declarations are similar. This is in stark opposition to VDHL that has a syntax that is distinct from anything other language I've ever seen. Then VHDL really contains 2 languages in itself, concurrent and procedural, which for whatever reason have completely different syntax. I still find myself on occasion referencing the syntax for some parts of procedural. So actually learning the syntax, I give it to Verilog. It is familiar looking (I'm assuming everyone taking said class will at least have some background in C) and easy to catch onto. The real kicker for me to advise VHDL over Verilog is that VHDL is strongly typed where Verilog isn't. Being a beginning class, you can expect the students to make a lot of mistakes. VHDL will complain at compile time and just crash throwing out a million error messages. Verilog will happily try to run it if at all possible meaning you may not find the bug until you've searched through the simulation results which can take a while. This is something that can get prevented(ie. 4 bit addition being stored to a 3 bit variable or comparing an unsigned value to a negative) by VHDL strongly typed nature. At least for me, and probably most students, it's nicer to get the complaint when I compile it than it is to go search for an error in the output. Lastly, this I'm not as familiar with, but I understand that Verilog is more heavily used in industry whereas most government contracted stuff is done in VHDL. I don't know if this factors into your decision or not. So my suggestion, if the students seem competent and can avoid simple mistakes, either language will do but Verilog might be slightly quicker to learn. But if it seems that they will be error prone, VHDL is probably the better choice.

How about Haskell? (1) (1260658) | more than 5 years ago | (#28160111)

FPGAs, you say? How about prototyping in Haskell? Here [] is a link to some videos describing the process.

VHDL, then Verilog (0)

Anonymous Coward | more than 5 years ago | (#28160145)

VHDL has a lot harder learning curve than Verilog, so it would be better to learn VHDL in a classroom environment. Once you learn VHDL, Verilog is cake to learn. I can say this from experience.

I've heard going from Verilog to VHDL is a painful process. Either way you learn them though, make sure you know them both.

Rocky's Boots! (1)

Plumber, Programmer, (1170969) | more than 5 years ago | (#28160153)

I know it's a little "old school," but have you considered using Rocky's Boots [] ?"
It's been a few years since I used it, but I thought it was a great tool at the time.

VHDHell? (1)

s-orbital (598727) | more than 5 years ago | (#28160197)

As a computer Science major, I only had one class involving this sort of thing, and it used VHDL. We all hated VHDL, and though I've never even used Verilog, and have only seen if briefly, I've heard others say its much better to deal with the VHDL. But then again this is all from memories I have from 3 years ago, and like I said, I've never used Verilog, so take this with a grain of salt.

verilog is less of an obstacle (1)

scatterbrained (144748) | more than 5 years ago | (#28160203)

I assume the intent is to teach about how to get your logic into an FPGA, what the internal structures look like, how synthesis maps from language into implementation, etc.

Any good designer has a mental model of what logic is going to get synthesized by a particular snippet of code, I find verilog gets in the way of expressing that model a lot less than VHDL, so I would say verilog is a better choice, in that you can get to the subject you want to teach much faster. Way less time explaining all the VHDL verbosity just to get to a working example.

Anonymous Coward (0)

Anonymous Coward | more than 5 years ago | (#28160217)

Both. I'm an EE that has worked a little with both and frankly the subtle differences and blatant ones as well need to be covered to fully understand the concept of what an FPGA does. Yes certain markets have preferences, but it would be like teaching a computer scientist only one system. You can emphasize one, but dont screw the other over and forget it entirely. Plus the implementation of FPGA's is not simply a focus of the language. The use and design of FPGA based systems is more complicated than its language. You can make hardware do alot with different software ways. Not gonna lie, this is another holy war and everyone has their opinion. As a student the objective is to learn as much as possible and not simply "develop a preference" and teaching both puts the decision on the student as to which they prefer.

It doesn't matter...just pick one (0)

Anonymous Coward | more than 5 years ago | (#28160219)

Every camp has their proponents, so it doesn't matter. Just pick one, both work equally well.
I personally use VHDL right now, but at some other company, it was Verilog. You probably don't have time to mess with both if the whole point is to do FPGA, not learn a hardware language.

Handel-C (1)

chetbox (1335617) | more than 5 years ago | (#28160261)

I did a similar course about a year ago and we used Handel-C. Assuming your students have coded in C before they do not have to worry about picking up the syntax, but rather they can focus on the parallel aspects of embedded programming like parallel execution and channels. I found it adhered to ANSI C reasonably well and actually improved my knowledge of the hidden depths on data representation in C. It "feels" like using C but with a few Occam-inspired macros to help create parallel code. The similarity between C and Handel-C also helps to bring home concepts like recursion is not possible in hardware, but iteration is. Also the documentation is thorough and clear. The reason we were given for using Handel-C over VHDL was the difference in overhead of learning a new syntax and of lower-level programming. I guess the downside is that the resulting circuits are likely to be much less efficient than in VHDL.

Why use Handel-C when you can use the open source (0)

Anonymous Coward | more than 5 years ago | (#28160647)

When you can use the open source Its much better from my experience.

Again, Open source gives a better solution.

mixed mode all the way! (1)

yaksha (1137459) | more than 5 years ago | (#28160279)

As an undergraduate we studied both VHDL and verilog in our course. Actually students need to know both as there are options of writing VHDL code inside verilog code these days. Personally I prefer both.

Schematic Capture or Icarus Verilog (2, Informative)

OrangeTide (124937) | more than 5 years ago | (#28160287)

In many ways schematic capture is an easier first step. You can hold off on Verilog or VHDL until you have made every flavor of flip-flop yourself. If you can get logic that has a few to several dozen gates to work first, then you can consider an HDL. And it doesn't really matter too much. There are pros and cons to each, and different industries prefer different languages. Actually different regions of the world prefer different languages too. Verilog is extremely popular in Silicon Valley, but on the East Coast you will find a lot more people using VHDL.

Many who prefer one over another do so because of features for doing verification. Until you know what verification is all about you probably won't be able to make an informed decision.

This fact makes it easy for most people: Icarus Verilog [] is open source, free and multi-platform. And useful for doing verification work, and also is capable of generating netlists to use with your favorite Xilinx or Altera parts. I'm not saying it's amazing or anything, but it does have some advantages for a hobbyist doing small projects.

systemVerilog (0)

Anonymous Coward | more than 5 years ago | (#28160289)

I'll go out on a limb here: SystemVerilog . It is the obvious future of HDL for both RTL and verification

Check the maker (1)

thomasinx (643997) | more than 5 years ago | (#28160297)

I'm seeing a lot of people complaining about VHDL and praising verilog, but I've used both and I'd say that the difficulties encountered with one will be seen with both. A lot of these complaints are just people who did some programming in VHDL and hated it. Using an HDL is not like using a normal programming language, and getting over that hurdle is what will be difficult for most people.

As far as what to teach in the class, identify what hardware you are going to use first, and then look at the tutorials supplied by the company supplying the boards. Most companies (Xilinx, Altera, to name a few) have tutorials they supply to use on their boards, that you can use as a first-step in designing coursework. I would make the language decision after checking what is supplied by the company.


Neither (1)

nurb432 (527695) | more than 5 years ago | (#28160307)

No really. There are tools for us old timers that let you design at the gate level, and then will create the code for you.

Defense vs. Commercial (0)

Anonymous Coward | more than 5 years ago | (#28160335)

I would argue that it also depends on what industry you eventually see the students going into. While a lot of people may like verilog better (myself included), almost ALL defense/military systems are written in VHDL. Their claim is that VHDL forces coders to be more careful and prevents some errors commonly made in Verilog from appearing.

Verilog - larger market share and dangerous (3, Insightful)

xlr8_joe (1566467) | more than 5 years ago | (#28160345)

Having worked in Silicon Valley and in Europe I have lived through some great battles of Verilog vs VHDL. Even had an engineer reminding me just lack week why VHDL is better. The reason he though it better was because it would not have allowed a port size mismatch that lead to some strange waveforms when the Logic Analyzer was configured the way he imagined it should be. None the less, Verilog is used for more ASIC designs then VHDL. (Simply ask the tool vendors Synopsys, Cadence, Mentor.)

For me Verilog is closer to describing HW and allows an engineer to do what they want. It is like a sports-bike. It will get you there very fast and you can cut a lot of corners. But, watch out or you will be in a ditch pretty quick.

For students, it is most important that they learn HW design before learning Verilog or VHDL. They need to understand the parallel nature of HW, and should be familiar with state machines and Karnaugh map reductions. In general they should not be writing shifters with for loops. Both languages allow you to describe HW that looks OK in simulation and has a whole host of problems after synthesis. I would teach Verilog because the language will not force good design and the students will be forced to learn when their FPGAs have problems. VHDL, on the other hand, will provided training wheels that allows the user to not truly understand what they are doing and still pass the class.

VHDL == history (4, Informative)

whoever57 (658626) | more than 5 years ago | (#28160381)

There were very good reasons why people used VHDL in the past. Because VHDL was an open language before Verilog, the cost of VHDL tools was historically lower than Verilog tools. Since this cost was much more important to FPGA designers, VHDL tended to dominate the FPGA market.

On ASIC side, the first mainstream commercial synthesis tool was Synopsys and Synopsys chose to support Verilog before supporting VHDL. Amongst all the other NRE costs in designing an ASIC, the added cost of using Verilog tools (instead of VHDL) was not really significant. Also, tools to support large designs advanced initially as Verilog tools.

Fast forward few years and Verilog is now open, the cost differential has now disappeared. However, VHDL had a lot of features related to design validation that were not in Verilog. In VHDL you can read and write files. Such things as configurations are supported, etc.. This type of capability makes it easier to write a testbench in VHDL, while on the Verilog side, additional tools and languages are commonly used.

Fast forwards a few more years to today and now we have System Verilog. This gives Verilog the capabilities that it lacked in comparison to VHDL and probably more. The price of VHDL tools is the same as Verilog tools.

Summary: it's clear that the future does not belong to VHDL. It looks like System Verilog is the future, although there are other contenders. So, if the choice is between VHDL and Verilog -- pick Verilog.

How about Simulink from The Mathworks (0)

Anonymous Coward | more than 5 years ago | (#28160389)

we have been using Simulink with DSP builder (from Altera) and we are very happy with this framework. We've used both Verilog and VHDL and we fell that Simulink is the fastest way to get a project up and running on a FPGA. Only problem, it is not cheap...

Something completely different... (0, Troll)

Anne Thwacks (531696) | more than 5 years ago | (#28160411)

Schematic capture is the answer

A picture is worth a thousand words, and a schematic is worth 1,000 lines of VHDL Disclaimer:

I have been using Xilinx since the 1800 (approx 1980).

Re:Something completely different... (0)

Anonymous Coward | more than 5 years ago | (#28160773)

I think that the best solution is not to code in either VHDL or Verilog. Code in C!! You can use the open source solution They give an on-line compiler from C to Verilog which allows you to code in C and synthesize verilog code.

Re:Something completely different... (1, Insightful)

Anonymous Coward | more than 5 years ago | (#28160775)

But 1000 lines of VHDL makes for a really, really tiny design, far smaller than anything implemented in a modern FPGA in a modern product. If you're still using schematic capture, you must still be developing for CPLD-sized devices.

It doesn't matter (0)

Anonymous Coward | more than 5 years ago | (#28160421)

If you understand how to design hardware, either will get the job done. If you don't, both will give you crap.

Either (1)

rosasaul (1412829) | more than 5 years ago | (#28160435)

To be honest for a college level program I don't think it matters. I learned VHDL in school, but only use Verilog at work. Hasn't much impeded me. There's a mild learning curve but if you know one you know the concepts necessary to easily learn the other.

Once Verilog supported signed arithmetic... (1)

chrispitude (535888) | more than 5 years ago | (#28160509) was game over. I was a staunch believer in VHDL and its many features (generics, records, operator overloading, strong type checking). But once Verilog implemented proper signed arithmetic which didn't require tedious manual sign extension in the code, then I never looked back. SystemVerilog continues to push Verilog forward. gwait (179005) had the right idea - start with Verilog, and if you ever need to work with VHDL, you will have a much better idea of what aspects of the VHDL language you do and don't need to learn.

how about this approach (1)

Dolphinzilla (199489) | more than 5 years ago | (#28160537)

Personally we usually look for VHDL programmers instead of verilog - I would recommend focusing primarily on VHDL, touch on Verilog AND maybe expose the students to LabVIEW for FPGA's, or possibly Annapolis Micro's Corefire software just to show them that there are other approaches besides VHDL and Verilog

Either or Neither (2, Insightful)

kj_cmpe (1545321) | more than 5 years ago | (#28160605)

As other people have pointed out, the important thing is that neither Verilog or VHDL are sequential programming languages... They are hardware description languages, or could be thought of as parallel programming languages or simulation languages. In any case, students will make the biggest mistakes by: 1. Thinking that it's just like C/C++/Java/whatever, and 2.Using features of either language (which are both quite powerful), but that are unsynthesizeable.

Thus, an important part of any course on HDL should have a heavy focus on synthesizeable code, with many iterations of seeing not just the "right" way to do things, but why that is the right way and the alternatives wouldn't produce the same (presumably good) hardware as the alternative ways that look or seem similar.

There are many other languages to consider as well that may or may not end up being used widely in industry.. a sampling is...

Plus, there are many C-to-Verilog, C-to-VHDL or C-to-HW compilers out there that try to jump from sequential code with pragmas etc. to the HW....

In general, I would suggest thinking of this not as a language course, but as a hardware design course where the tools used happen to include a new language (for the students). It would be easy to concentrate on language syntax and end up with students that know syntax, but not how to make good HW descriptions....

For what its worth (1)

427_ci_505 (1009677) | more than 5 years ago | (#28160679)

I've only ever used VHDL, but it is fairly clean and easy to get started with.

I suppose I should have given Verilog more of a chance, but I just ran away screaming whenever I opened up a *.v file.

learn digital design, then learn syntax (2, Insightful)

rsw (70577) | more than 5 years ago | (#28160703)

I work at a mixed signal IC company that is, on the digital side, principally a Verilog shop. We do have one or two projects that use VHDL, and maybe even one or two that use both. From a practical applicability point of view, Verilog is a bit more popular as far as I know, but this should not be taken to imply that you will do your students a disservice teaching them VHDL. When we interview digital designers, we don't ask them "do you know Verilog?" we ask them "do you know digital design?" The language is far far less important than the underlying concepts.

The biggest mistake you can make is concentrating on the language and expecting the programming skills will apply to digital design just because the syntax of Verilog looks like the syntax of C (or VHDL looks like Pascal, if you squint a lot). First, learn how to do digital design, then learn how to describe those designs in an HDL. Things might go slightly faster if you are familiar with the syntactic structures (i.e., C coders will feel more comfortable using Verilog), but trying to take the "do-while--if-then-else--for" mentality of a procedural coder and trying to jam it into an FPGA is going to be a painful road to failure.

It's time for a bad analogy! "Hey guys, I have a bunch of novelists whom I want to teach to write medical textbooks. Should I teach them to do it in English, or Spanish?" The answer is "whichever they're more familiar with already... but first teach them medicine."


This is not CS (1)

Sybert42 (1309493) | more than 5 years ago | (#28160715)

/. is mainly CS.

System Verilog (2, Interesting)

alain94040 (785132) | more than 5 years ago | (#28160761)

If your goal is to prevent the students from ever completing their project and running on real hardware, then pick VHDL. Its ADA-like compiler will reject every possible attempt at coding until you master the language.

At least with Verilog you'll compile some gates, which may or may not work functionally, but at least you'll have fun discovering what your code does in hardware.

I was part of the IEEE committee which standardized the VHDL subset for synthesis (a fiasco, but that's another story).

10 years ago, the debate between Verilog and VHDL was that the US was using Verilog and academia and Europe were using VHDL. That's over: pretty much everyone switched to some form of SystemVerilog.

In the end, what really matters is that students can go back and forth between any given language construct (blocking assignment, missing assignment, for loop, etc.) and its hardware equivalent (flip-fop, latch, mux, etc.).

Very few people are good at this. The ones that do make $150,000+ in Silicon Valley. So it is definitely a good career path.

Verilog 100% No Question (2, Insightful)

Murdoch5 (1563847) | more than 5 years ago | (#28160811)

Verilog, I've had to program FPGA's and CPLD's and the one thing I can say for sure is VHDL is the worst programming lanugange of all time. It's syntax is horrible, it's keywords are non sense, it's declerations are crap, all in all it's horrible.

Vhdl solves 0 problems with helping a student learn hardware design. From a personal note I don't think anyone should use FPGA's / CPLD's. They don't solve a single problem that can't be done in pure software. Future more what use is it to say make a Train program on a FPGA / CPLD. There is real use for these hardware device.

My prof made it sound like they were the most important devices in the world and I have to disagree with him completely. I would understand 5 - 10 years ago when we simply didn't have the hardware preformance we have now, then a FPGA / CPLD could be useful.

Well VHDL might have a ton of existing libs for it and it might be reconized widely, it's still a horrible and hidious method of hardware design period. We had to do many labs this year using it and really there was no time saved, NONE, and from what we were taught it would make the job easiler!

After spending 4 months with VHDL and then 1 week with Verilog, there's no completion. Verilog is a much much better method of programming FPGA's / CPLD's. Hands down it wins, it's like asking which is better for programming a airport system , Hand Assembling the software using ATT&T syntax in Windows Debug (VHDL) or using C (Verilog). All the labs the entire class did were preformed 1000x faster in Verilog with a much higher level of understanding.

If you have to pick, it's not a question just and answer it's Verilog all the way. VHDL has to retire, it's of no use, it's horrible to work with, it's horrible to use and forget trying to understand it to a decent level. Verilog is very nice to work with and it omits many of the down falls of VHDL.

I would also like to add that doing FPGA / CPLD design is also becoming rather pointless, with the advances in modern computer programming languages and compiler, it's no longer a case of not having a fast software solution. The hardware and the software are no longer seperated by such a huge amount, well there might be a slight and I mean maybe 1 - 5% increase in preformance using a FPGA / CPLD I don't think that becomes enough of a reason for using them anymore. At least not in college and university programs, doing labs where you have to program a game like Tetris or Space Invaders, what does that teach you. What it does is waste hours and hours of dealing with problems and bugs and crappy syntax do get something that doesn't satify any need.

All in all I think the FPGA and the CPLD,except in special cases, have served there purpose and are no longer a good solution to computer and electronic design. Unless someone can make a hardware desciption language that can actually make sense and flow, the FPGA and CPLD's are done.


A University Student's perspective on VHDL... (2, Informative)

file_reaper (1290016) | more than 5 years ago | (#28160825)

We were introduced to VHDL in our University's Digital Circuits course.

Most of the above commenter's have mentioned that Verilog is C like, I personally have never used or programmed in Verilog so I can't comment on that.

I did however like VHDL very much, particularly because it was *different* from C, I'm kinda growing tired of C like languages and VHDL was a breath of fresh air. It made FPGA's and the entire course in general a whole lot of fun.

It's strong typed nature was a bit cumbersome at first especially with converting std_logic to std_logic vectors and such because we weren't really shown how to do this or given a syntax/library reference like MSDN or Java's Documentation site.

So I'd say make a good introduction to Entities, Ports and Architectures, explain Process, Signal and Constant statements very well, also particularly highlight the strong typed nature of VHDL.

I think most of your students (such as myself) will not have done any programming in a true strongly typed language before, so this will be bit of a shock, and getting those conversions will be frustrating. (I have been there, Googling really does not help all that much)

I hope your students get as much fun out of that course as I did.


Probably Verilog (2, Informative)

davebaum (653977) | more than 5 years ago | (#28160837)

VHDL and Verilog each have their strengths, which is why neither has been able to supplant the other. Perhaps in the long run System Verilog will change this (bringing much of the power of VHDL to the Verilog world), but that day hasn't arrived yet.


Verilog code tends to be very concise, with the language making some implicit conversions and assumptions that turn out to be correct most of the time.


VHDL is bigger, bulkier and more rigid. The rigidity can be annoying, but it also is good at catching errors. The language has features that allow for very elaborate testbench construction, and some powerful means for abstraction (the generate statement, multiple architectures for an entity, etc). But this power comes at a cost. The spec for the language is several times larger than for VHDL. At one point I had a Verilog quick reference that fit nicely on a single page. My equivalent quick reference for VHDL covered four pages.


I've gone through the "choose an HDL" process twice, and both times selected VHDL. But that was within the context of at least half the team already being fluent in VHDL, and working on a large enough (and long lived enough) codebase that we could take advantage of some of VHDL's power. I wish VHDL wasn't so cumbersome and verbose, but it was still a win overall.


You are in a very different situation. I'm assuming you have minimal experience with either language, and it will be new to your students as well. You're going to have plenty of other things to be worrying about (digital design, synthesis, debugging, etc). I think Verilog is a better choice for your situation. It's going to do everything you need, and not really get in your way.


Also, don't worry about which tool is more popular in industry. Tools change many times over a career. University classes should be about providing good theory and foundation, so pick whatever tool enables you teach those concepts most effectively.

Verilog is the future (0)

Anonymous Coward | more than 5 years ago | (#28160881)

VHDL is the best bet if you are doing professional FPGA design, especially in the gov't/mil/aero/space industries. There is a lot of legacy code in VHDL and you're more likely to buy IP cores in VHDL. It is quite wordy, but the strong typing saves debugging time.

But for hobby or commercial use, Verilog is the clear winner. Verilog has much better FOSS tools (I never could get isim or freehdl to work right, and I do this for a living). The openHPSDR firmware is all in Verilog. The weak typing makes Verilog easier to learn, and it's more compact. System Verilog is a fantastic advancement and offers much that VHDL doesn't. I suspect everyone will be writing their testbenches in system verilog (or perhaps SystemC), even if the synthesizable code is in VHDL. Might as well learn just one language and do everything in Verilog.

Schematic capture will limit you; it's fine for small-time hacking but if you really want to learn this stuff you can't beat an HDL. Also be careful about graphical tools like LabView, CoreFire, Simulink, etc for FPGA design. You'll end up only understanding that one proprietary design entry language and won't be able to share designs and knowledge with the broader world.

go verilog (1)

Khashishi (775369) | more than 5 years ago | (#28160883)

VHDL is powerful but is too general. Basically, you can make the language do whatever you want, (not just limited to gate code, but any sort of modeling or computation, period), but it's a pain in the ass to do it. Pretty much all the operators and symbols (even '1', '0', 'h', etc) need to be defined before you can do anything, making it a feat to actually get work done. Well, there are standard libraries for stuff, but there are issues with multiply defined symbols and stuff in different libraries.

VHDL is very verbose and requires a lot of boilerplate code to do the simplest tasks. That said, it does scale reasonably well.

I think Verilog is more specifically geared toward FPGA gate code, and so it's a lot simpler to use. You don't have to fight the language like in VHDL. Go Verilog.

(Structural) Verilog (1)

Roguelazer (606927) | more than 5 years ago | (#28160887)

I've found that Verilog is much easier to learn and teach (at least, for an undergraduate engineering-type class). But, as others have mentioned, do NOT think of it as a programming language. Think of it as a convenient way to draw schematics, a very sophisticated keyboard layout for Xilinx. You should ALWAYS write synthesizable code for everything except your testbench, and you shouldn't have to synthesize it to know what it looks like. As to why not VHDL, well, VHDL is the COBOL of HDLs. Way too verbose for me.

Personally I'd go for verilog (1)

petermgreen (876956) | more than 5 years ago | (#28160919)

VHDL has an incrediablly anal-retentive type system and has some silly ideas like the splitting of entities and architectures. It's also old meaning you need a lot of boilerplate to manually import STD_LOGIC stuff (which is what the synthisis tool vendors tell you to use for everything)

Whichever you use be aware that both VHDL and Verilog weredesigned as hardware simulation languages not hardware synthisis languages. This means it is vital to get to know the synthisis tool you will be using. It is vital to know what warnings matter and what can be safely ignored and which are important, what parts of the language must be avoided, how to assign clocks to clock nets, how to use the timing analyser (without timing alalysis you don't know if your code will actually work) and so on if you are going to use the languages for FPGA programming.

Load More Comments
Slashdot Login

Need an Account?

Forgot your password?