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Building Complex Circuits With Carbon Nanotubes

Soulskill posted more than 4 years ago | from the series-of-nanotubes dept.

Science 42

Lorien_the_first_one writes "MIT's Technology Review reports that carbon nanotubes are being used to fabricate complex circuits. From the article, 'The first three-dimensional carbon nanotube circuits, made by researchers at Stanford University, could be an important step in making nanotube computers that could be faster and use less power than today's silicon chips. Such a computer is still at least 10 years off, but the Stanford work shows it is possible to make stacked circuits using carbon nanotubes. Stacked circuits cram more processing power in a given area, and also do a better job dissipating waste heat.'"

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42 comments

Cool! (1)

flyneye (84093) | more than 4 years ago | (#30633098)

So I could have a cluster the size of my wallet with the keyboard and monitor dwarfing it.

Re:Cool! (-1)

Anonymous Coward | more than 4 years ago | (#30633516)

Imagine a beowulf cluster of wallets!

Re:Cool! (1)

ceoyoyo (59147) | more than 4 years ago | (#30637228)

You can already have a cluster the size of your wallet, with the keyboard, monitor, packaging, cooling apparatus, interconnects, etc. dwarfing it.

Heat dissipation (1)

TheLink (130905) | more than 4 years ago | (#30633100)

How do stacked circuits do a better job of dissipating heat than a flatter circuit that can dump heat to a heatsink on at least one side?

Re:Heat dissipation (1, Interesting)

Anonymous Coward | more than 4 years ago | (#30633192)

carbon tube are heat resistent, you do no need to cool them.

Re:Heat dissipation (1)

John Hasler (414242) | more than 4 years ago | (#30633200)

> How do stacked circuits do a better job of dissipating heat...

They don't, nor does the article claim that they do. The low power dissipation of carbon nanotubes allows the circuits to be stacked.

Re:Heat dissipation (1)

Turzyx (1462339) | more than 4 years ago | (#30633296)

From the article (first paragraph), and the summary

Stacked circuits cram more processing power in a given area, and also do a better job dissipating waste heat.

Re:Heat dissipation (2, Funny)

Geoffrey.landis (926948) | more than 4 years ago | (#30633808)

> How do stacked circuits do a better job of dissipating heat...

They don't, nor does the article claim that they do.

Darn, where's that "-1: did not read as far as the last line of the summary" moderation option when I need it???

Re:Heat dissipation (0)

Anonymous Coward | more than 4 years ago | (#30633210)

I believe part of the theory is that if you can make a 3 dimensional circuit, you can incorporate either air or fluid pathways into it so it acts as a direct heatsink.

Re:Heat dissipation (1)

ShooterNeo (555040) | more than 4 years ago | (#30633338)

Still would be easier to have a 2-dimension circuit with a fluid pathway on one or both sides. Stacking circuits does allow for a lot greater density...it's obviously what we'll eventually use...but the heat problem means that we won't be doing it with current materials for CPUs. (for memory chips it would work fine)

Re:Heat dissipation (3)

vlm (69642) | more than 4 years ago | (#30633362)

How do stacked circuits do a better job of dissipating heat than a flatter circuit that can dump heat to a heatsink on at least one side?

The article didn't mention any heatsink limitations, or at least firefox didn't find that word. Some weird fractal shaped device with a bunch of sides? Of course the minimum volume design would be a sphere, which has minimum surface area per volume, kind of counterproductive.

My guess is going 3-d allows the heat generation of the whole die to approach the max... Rather than having regions that run hot and regions that run cold, with the limit of the whole device being the hottest little part, you could spread the hot parts around the die, in theory maybe every little portion of the die could dump exactly the same amount of heat, for a given workload anyway...

Re:Heat dissipation (1)

Ceriel Nosforit (682174) | more than 4 years ago | (#30633936)

A matter flow could transfer the heat to a sink. With this level of technology it seems cost-effective.

Other than that, aren't the nannytubes slightly supraconductive or something? X-box hueg electron mobility, the internet told me. Shouldn't be there be much less powerloss this way?

And while I'm on it, a little bird told me that according to the physics only erasing bits 'costs' energy. Some real-world CPU design allows the system to return to any previous state by running backwards, since it hasn't erased any bits.

Did I just outline the theoretical limit for non-quantum computers?

Re:Heat dissipation (1)

Nefarious Wheel (628136) | more than 4 years ago | (#30635326)

Can carbon nanotubes be made large enough in diameter to effectively pass another fluid through them for better heat dissipation? Doesn't have to be liquid, and you don't need closed plumbing, the nanotube elements would just need to be open at both ends. Simple convective gas recirculation might be enough for the inner layers. Perhaps. Maybe.

Re:Heat dissipation (1)

Khyber (864651) | more than 4 years ago | (#30638184)

"The article didn't mention any heatsink limitations, or at least firefox didn't find that word. Some weird fractal shaped device with a bunch of sides?"

I'm no material physicist, but diamonds are formed from carbon, under very high heat and very high pressure. I think it would make sense that these could probably withstand far more heat than silicon-based devices if built with a crystalline lattice, and also to disperse it given how readily conductive some forms of carbon are known to be. This is really just the ultra-precise manufacturing of nanoscale diamond, from just a pure chemical pov, it seems.

Re:Heat dissipation (1)

Bigjeff5 (1143585) | more than 4 years ago | (#30633506)

Stacked circuits are going to have more total volume in contact with whatever medium they are using to dissipate heat than a flat circuit would. Flat = 2 dimensional, stacked = 3 dimensional. These circuits probably aren't just going to be sitting around in the air.

Look at your CPU, which is encased in material, not your motherboard which is open to the air. The big heatsink on the CPU is just dissipating the heat away from the medium that is absorbing the heat off the silicon in the first place.

It's important to note here that modern CPU's aren't flat either. They certainly LOOK flat, but the circuits are stacked hundreds of layers thick. A scanning-electron microscope view of a silicon wafer looks like a sort of futuristic city. It's pretty damned impressive.

Re:Heat dissipation (1)

taniwha (70410) | more than 4 years ago | (#30633800)

maybe 'tens of layers thick' for still small to medium values of 10s - there may be 100 or more steps to create those tens of layers though

Re:Heat dissipation (1)

khallow (566160) | more than 4 years ago | (#30635928)

Stacked circuits are going to have more total volume in contact with whatever medium they are using to dissipate heat than a flat circuit would. Flat = 2 dimensional, stacked = 3 dimensional. These circuits probably aren't just going to be sitting around in the air.

Why would "flat" circuits be cooled in 2-D? Reading around, it appears that carbon nanotubes are simply really good at conducting heat and generate a bit less heat for the same activity. So a 3-D structure of nanotubes would be easier to cool than the corresponding structure of silicon performing the same activity.

Re:Heat dissipation (1)

loose electron (699583) | more than 4 years ago | (#30636786)

Depending on the foundry process, typical CMOS has between 8 masks and 16 masks (aka reticles) for the base layer fabrication of transistors. Metal interconnect layers on top of that vary between 1 (very rare) and 20 (also pretty rare) - commonly between 4 and 8 metal layers

Re:Heat dissipation (1)

miggyb (1537903) | more than 4 years ago | (#30636742)

If you're going to make a 3D processor, you might as well just integrate the heatsink, no? Build it with a large surface area and just dip the entire thing in copper... (IANAE)

Re:Heat dissipation (1)

Khyber (864651) | more than 4 years ago | (#30638192)

Copper and silicon don't react very well together, this is what has effectively stopped us from using copper more extensively in processors, thus we use gold, which is far less reactive of a material, plus it doesn't oxidize like copper.

Re:Heat dissipation (1)

Grishnakh (216268) | more than 4 years ago | (#30646584)

I haven't read TFA, but I think part of the problem is that silicon, which conventional circuits use as a substrate, is a poor conductor of both heat and electricity, which is why it isn't usually stacked. Do these new carbon-nanotube circuits still use silicon as a substrate? Maybe they have a substrate that's more thermally conductive.

So this means 3-D processors, right? (1, Interesting)

Anonymous Coward | more than 4 years ago | (#30633278)

What is this going to change? I guess it would be easier to update the designs because you don't have the 2-D crosspath issue anymore. And you should also have shorter distances between components. Is there anything else significant?

Re:So this means 3-D processors, right? (3, Informative)

LordofEntropy (250334) | more than 4 years ago | (#30633350)

From the FA:

"A recent IBM study showed that for a given total power consumption, a circuit made from carbon nanotubes is five times faster than a silicon circuit"

And:

"The Stanford group is currently working to make ever more complex integrated circuits. "So far as complexity is concerned, there is fundamentally no barrier" on carbon nanotubes, says Mitra."

So at least in theory not only can the designs be updated as you mentioned, but they should be able to get pretty crazy with said designs.

Re:So this means 3-D processors, right? (2, Interesting)

vlm (69642) | more than 4 years ago | (#30633474)

What is this going to change? I guess it would be easier to update the designs because you don't have the 2-D crosspath issue anymore. And you should also have shorter distances between components. Is there anything else significant?

Without the limitations of 2-D interconnects, you could:

build barrel rollers / barrel shifters in the shape of a barrel...

http://en.wikipedia.org/wiki/Barrel_shifter [wikipedia.org]

build ring oscillators and ring counters in the shape of a ring...

http://en.wikipedia.org/wiki/Ring_oscillator [wikipedia.org]

Currently, using 2-D techniques, you can easily build on-die flat arrays of parallel processors. With 3-D, I guess you could build on-die 3-D arrays of parallel processors. Still out of luck for hypercube (4-D) architecture, although wiring might be somewhat simpler..

Great for clock wiring (1)

marcosdumay (620877) | more than 4 years ago | (#30642462)

Clock distribution may be must easier when you don't have to be concerned about changing layers and not crossing other wires while keeping the wire length under control. Anyway, that is just the tip of the iceberg...

Re:So this means 3-D processors, right? (1)

jimbolauski (882977) | more than 4 years ago | (#30633972)

Carbon nanotubes show more promise in the shrinking transistor race, they do not require as much electricity at the same size when compared to silicone. Currently the carbon transistors can be made but quality control is lousy, nobody can get them to grow in a predictable manor, Stanford has found a way to test each individual transistor on the wafer and only connect the ones that are aligned. Because less energy is used there will be less heat and the circuits can be stacked.

Apples products (0, Funny)

Anonymous Coward | more than 4 years ago | (#30633328)

Sometimes I think i'm bi-curious.

Although I've never actually bought an apple product, I can't completely rule it out, if the right product comes along.

size matters (1)

DinZy (513280) | more than 4 years ago | (#30633420)

The size of the chip on the actual wafer can be reduced with 3d chips giving more chips per wafer. The downside is that there are more process steps per wafer as a result. Overall I think the 3D chip design only makes sense if you get to do it with different materials like CNTs like in this article. I am so curious to see what happens in the next 10 years.

Where have we seen this before... (1)

Anonymous Coward | more than 4 years ago | (#30633430)

Oh, right. Miles Dyson, Skynet, Terminators.

So in 10 years? (4, Informative)

gmuslera (3436) | more than 4 years ago | (#30633434)

Looks like 5 [xkcd.com]

Re:So in 10 years? (3, Interesting)

Interoperable (1651953) | more than 4 years ago | (#30633898)

Very true, 10 years seems very optimistic considering the colossal challenges of reliably growing nano-tubes. The technique presented in the article offers a way to work around defective (conducting) nano-tubes rather than eliminate such defects. The research done here is very interesting, but processors need to be stamped out by the millions; a technique that requires manipulation of tubes that is customized to each circuit based on random yields simply can't be scaled up into full production.

Before nano-tube processors come out, the defect rate would have to be low enough that most processors have zero (or few) defects rather than each requiring careful tuning of each gate to get them functional. I think this is a case where there will be a big gap between the proof-of-principle functional gates in labs and a marketable product. Still, the prospect of three-dimensional nano-tube processors is very exciting even if it's a long way off. The work presented in the article is also very interesting and is certainly a clever technique, even if it may not find commercial application for a long time.

Re:So in 10 years? (1)

Hazelfield (1557317) | more than 4 years ago | (#30635054)

I'm not sure about that. I think in the future, the OS might have to deal with a lot more computing errors and fault tolerance. It could be better to accept a few broken transistors and use some sort of redundance algorithm if you get vastly greater computing power in the deal.

I completely agree though, that the 10 year prospect is very optimistic. The semiconductor industry evolves at a rapid pace, but this isn't evolution, it's revolution. It will take time before the first usable chip is made with this technology, and it will take even longer before those circuits can compete with silicon-based circuits.

Re:So in 10 years? (1)

txoof (553270) | more than 4 years ago | (#30637144)

At least it's not 20 years off like fusion and flying cars. Where is my damn auto-piloting flying car that I was promised to me when I was a kid? I can still remember watching some PBS special about auto-drive cars and how they're only 10-20 years off.

I also would like to know where the hell my quantum computer is. I ordered that thing right about 10 years ago and it still hasn't shown up. I want my money back and you damn kids better get off my lawn!

Re:So in 10 years? (0)

Anonymous Coward | more than 4 years ago | (#30638980)

Auto-drive cars are not here because they are stupid and don't solve any problem. Technical problems were solved in the nineties.
People want to control the cars they own(that's stupid too, by the way).
It would be cheaper, more environment friendly and less congestion prone to build a public transportation infrastructure over our roads, using materials from recycled cars, but then we would be Communists or something and thus we need to put 3 ton killing machines in the hands of people barely able to tie their own shoes'.

Re:So in 10 years? (1)

oldhack (1037484) | more than 4 years ago | (#30634366)

Bleh. Throwing together "carbon nanotube" with "at least 10 years" - the nerve of these people.

3 dimensional CPUs could increase performance (0)

Anonymous Coward | more than 4 years ago | (#30633922)

With traditional processors, a greater portion of the processor has to be further away from its center. I would assume this means that this slows down computation, when looking at the big picture.

With 3D though... It makes sense to me that adding height creates a whole new way to reorganize a processor. Pathways can be shortened not only on their X/Y axes as currently done, but additional condensing could be done on the z axis as well. I would theorize that creating a CPU with the most 'useful' pathways closest to where they need to be would yield the best performance and generate less heat, where we would have far fewer options to optimize a processor like this on the 2D plane.

progress, kind of (2, Informative)

Goldsmith (561202) | more than 4 years ago | (#30634488)

These are more or less the same techniques we used in carbon nanotechnology 10 years ago. The difference is that now there are more than 2 or 3 groups capable of mastering all these techniques. It's nice to see everyone hasn't given up on this material and that engineers have taken over now that all the scientists have moved on to graphene. It's still far too expensive to make transistors from carbon nanotubes, but maybe they're right and these labor-intensive techniques used can be automated.

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