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Cheaper, More Powerful Alternative To FPGAs

timothy posted about 3 years ago | from the even-more-field-programmable dept.

Hardware 108

holy_calamity writes "Technology Review takes a look at a competitor to FPGAs claimed to be significantly faster and cheaper. Startup Tabula recently picked up another $108m in funding and says their chips make it economic to ship products with reconfigurable hardware, enabling novel upgrade strategies that include hardware as well as software."

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108 comments

Me like (0)

Anonymous Coward | about 3 years ago | (#35835160)

I'd like a cheap alternative to FPGAs but the whole notion of hardware upgrades through programmable circuitry is pretty flawed.

Re:Me like (3, Interesting)

jamesh (87723) | about 3 years ago | (#35835594)

For sure. Don't worry about getting the hardware working exactly right, we'll ship it now and release an upgrade later.

FPGA for designing ASICs, or small-volume chips (2)

billstewart (78916) | about 3 years ago | (#35835716)

If you're designing an ASIC, one traditional method is to do your design, flash it to FPGA, test it, debug, repeat, and when you're done, send it out to the fab to get it burned into ASIC. So yes, it's hardware upgrades through programmable circuitry, and you might be doing multiple upgrades per day.

If you're doing small production runs of chips, for instance for custom hardware, you may want something that's fast but you're not going to make 10,000 of them so you don't want to pay the price of burning ASICs. (ASIC prices have gotten a lot cheaper in the last decade, and production cycles have gotten faster, but it still takes time and money.) So don't - just do the chip in FPGA. And just like providing firmware in EPROM, the fact that the chip's reprogrammable doesn't mean you'll necessarily be doing that in the field.

These guys are basically doing a smaller cheaper FPGA design, as far as I can tell from the article and the comments. Those sound like good things.

ASICs got more expensive! (2)

tempmpi (233132) | about 3 years ago | (#35836492)

ASICs actually got more expensive. The individual ASIC is cheaper now, but the non recurring costs of making a ASIC went up a lot. Smaller process nodes need more masks and more complicated masks.
If your mask set is $2.000.000 and you are going to sell ASICs 10,000 made with it, even if the individual ASIC is free after paying for the masks, you are still at $200 per piece. The $100 FPGA is a better option then and at 10.000 pcs you are going to get a pretty large fpga for $100.

Re:ASICs got more expensive! (3, Informative)

julesh (229690) | about 3 years ago | (#35837622)

ASICs actually got more expensive. The individual ASIC is cheaper now, but the non recurring costs of making a ASIC went up a lot. Smaller process nodes need more masks and more complicated masks.
If your mask set is $2.000.000 and you are going to sell ASICs 10,000 made with it, even if the individual ASIC is free after paying for the masks, you are still at $200 per piece. The $100 FPGA is a better option then and at 10.000 pcs you are going to get a pretty large fpga for $100.

Sure. But the older processes are still available. I haven't looked at pricing for a few years, but IIRC last time I digged into this, $2M was about the right price for preparing masks for 65nm processes. However, if you went for something a few process steps older (e.g. 0.35 or 0.5 micron processes which are still readily available), you'd be looking at somewhere in the region of a hundredth that price. And a 0.35um CMOS ASIC can perform similarly to a 65nm FPGA: on both you'd expect non-trivial designs to operate with clock frequencies in the region of low hundreds of MHz.

Re:ASICs got more expensive! (2)

tempmpi (233132) | about 3 years ago | (#35838328)

If you care only about logic of the FPGA that might work, but the FPGA isn't just logic but also IO cells, SERDES, builtin memory controllers, ram resources etc.
Because of that you can't replace the FPGA with a ASIC manufactured in a many generations older process, two or three process nodes is fine and you can use a gate array process to lower the mask cost.
But that doesn't fundamentally change the problem: For low volume products FPGAs are cheaper than ASICs. These days you need a pretty big volume to make the switch to a ASIC profitable. FPGAs are used in mid volume consumer products these days.

Re:Me like (1)

rtb61 (674572) | about 3 years ago | (#35836430)

Add to that, security becomes a real nightmare, when you can no longer trust you hardware.

Seems pointless to replace the CPU with a programmable chip but certainly putting the OS onto a programmable chip seems like a worthwhile exercise, certainly ramp up boot times and drive compact OS's.

Re:Me like (0)

Anonymous Coward | about 3 years ago | (#35838446)

you trust your hardware?

Re:Me like (2)

roc97007 (608802) | about 3 years ago | (#35835832)

I think the biggest flaw is that manufacturers don't necessarily want to update your existing device -- they want you to buy a new one. So whether the technology exists affordably really doesn't matter.

Re:Me like (1)

fuzzyfuzzyfungus (1223518) | about 3 years ago | (#35836756)

Oh, I'm sure that they'd be happy enough to sell you the update and skip the hassle of actually producing a new unit. Particularly with all the delightfully DRM-y advances in bootloader-level cryptographic verification and so forth, I could easily see a modern version of the old 'golden screwdriver' upgrade being employed.

(Even without reconfigurable hardware, it is hardly out of the ordinary among 'enterprise appliance' type hardware to pay nontrivial money for unlock codes that let you use parts of the system that the system shipped with. If that model can survive, hardware upgrades through software would look downright sensible by comparison.)

Re:Me like (5, Informative)

gmarsh (839707) | about 3 years ago | (#35836186)

Here's the thing people don't seem to realize: FPGAs *are* cheap.

Case in point: Xilinx XC3S50A. $5.75 at Avnet. Comes in a hobby-solderable VQFP and you can make it work on a 2-layer board. Add a SPI flash to boot from (or a nearby micro with ~50K of spare flash), an oscillator, and +3.3V/1.2V regulators for power and you're still under 10 bucks parts cost - in low quantity.

This chip is only bottom of the line, but it's full of awesome stuff - "DCM" clock multipliers that can let you run FPGA designs at 250+ MHz by multiplying up slow external clocks, three 18x18 multipliers that run at almost the same speed, three 2Kbyte SRAM blocks that you can use as instruction/data memory for processors (eg, a Picoblaze, which can run at 100+ MHz).

These are great little things to play with as a hobbyist. I've contemplated making an Arduino shield with a small, cheap FPGA for people to experiment with, but I never really could figure out any good way to get data and signals in and out of the chip in a way that shows off what FPGAs are really good at.

Re:Me like (3, Interesting)

hairyfeet (841228) | about 3 years ago | (#35836578)

How about audio processing? Are they any good at that? Because anything really customizable seems to cost an arm and a leg when it comes to musical gear. You could write a plugin for Audacity that interacted with it, maybe letting guys like me offload some of the processing on effects?

If there is one place that F/OSS could really take some serious marketshare it would be musical creation. Most of us musicians have no problem with tinkering, and as long as we can do cool things with it we don't mind if we have to get a little fiddly, and finally Audacity is already F/OSS and frankly is pretty kick ass, so there is already great software to plug these things into. If these chips would work good for audio I could see F/OSS DIY home studios becoming hot with musicians, especially seeing as how crazy the prices for some of the proprietary stuff is.

Re:Me like (1)

bobbozzo (622815) | about 3 years ago | (#35837544)

DSPs (good for audio processing, among other things) can be (and often are) implemented in FPGAs, however I assume you'd need a 16 or 24-bit implementation for high-quality audio.
I don't know how much an FPGA capable of that would cost, but there's lots of info online so it must be reasonably affordable.
http://www.google.com/search?q=fpga+dsp+audio [google.com]

They are (1)

Weaselmancer (533834) | about 3 years ago | (#35836670)

Here's the thing people don't seem to realize: FPGAs *are* cheap.

They are. I do embedded design for a living. And I'm yet to see a design cross my desk that doesn't have a Xilinx or Altera chip on it. You see them typically used as glue logic, like buffers in between the cpu and pcmcia slot. Or clock generation. Discrete components for that would be *far* more expensive.

FPGAs are already a bargain. Sure, if something cheaper and faster comes along that'll be great. But not really necessary.

Re:Me like (Running FPGA Examples) (1)

Required Snark (1702878) | about 3 years ago | (#35836698)

Here are some running FPGA projects that are Arduino related:

http://papilio.cc/ [papilio.cc] Home of the Papilio FPGA board, which has a similar intent to the Arduino. It currently supports a stack CPU and an AVR emulating CPU. The AVR CPU supports the Arduino tool chain. Here is another site for projects with this board. http://gadgetforge.gadgetfactory.net/gf/ [gadgetfactory.net]. You can get it for $US 50 or 75, depending on the FPGA size.

The Gameduino http://excamera.com/sphinx/gameduino/ [excamera.com] is an Arduino shield with an FPGA that supports sprite graphics for old school game play. The FPGA code includes a Forth engine that runs as 50 MHZ. Programming is done on both the Arduino and the FPGA board.

Re:Me like (1)

davFr (679391) | about 3 years ago | (#35837514)

"Xilinx XC3S50A" : of course, that's the very low-end line-of-product from Xilinx. Additionally, Spartan 3 is an old generation.

On the other hand, check the price of large, high-speed FPGA from Xilinx's Virtex 6 family : nothing below $1000. Top at $10000.
Ouch.

http://avnetexpress.avnet.com/store/em/EMController/Programmable-Logic/FPGA/_/N-4294649145%204294609580%20100235?Nn=25&action=products&cat=1&catalogId=500201&cutTape=&inStock=&langId=-1&myCatalog=&proto=&regionalStock=&rohs=&storeId=500201&term=&topSellers= [avnet.com]

IMHO, Tabula is targeting the market of large, high-performance, FPGA matrices.

FPGA is nice but not a magic bullet. (1)

GlibOne (1203032) | about 3 years ago | (#35835210)

I do not think the FPGA works the way they think it works. For instance an ARM processor is going to be faster less power hungry then a FPGA programed as a ARM processor. It can't grow a blue-tooth or a GPS etc. The FPGA is also in the same improvement cycle as any other part so the newer phone will have the better FPGA. I am not saying having one in there is bad it is nice for tweaks to the system but it is not a magic bullet.

Re:FPGA is nice but not a magic bullet. (1)

peragrin (659227) | about 3 years ago | (#35835300)

It can't grow bluetooth, or gps, yet.

it can become the receiver for either though. which means all you really need to do is to setup multiple antenna's that can be lengthened/shortened as needed.

Now there's an experiment that needs more research. how do design an "modular" antenna so that you can change which frequencies are received/transmitted allowing for a truly broad spectrum operations.

Re:FPGA is nice but not a magic bullet. (3, Informative)

GlibOne (1203032) | about 3 years ago | (#35835398)

See Fractal antenna [wikipedia.org] no multiple antenna's needed. The receiver part is a different story.

Re:FPGA is nice but not a magic bullet. (1)

Anonymous Coward | about 3 years ago | (#35835454)

See plurals [wikipedia.org], no apostrophe required.

Re:FPGA is nice but not a magic bullet. (1)

RaymondKurzweil (1506023) | about 3 years ago | (#35841342)

It can't grow bluetooth, or gps, yet.

Well, there are devices that can, which are basically just slightly "better" PSoCs .

That's not the point. It doesn't seem like FPGA/PSoCs could ever be as cheap as a dedicated solution. Even if there is a breakthrough in fab that makes FPGAs closer to their dedicated counterparts, those efficiencies should also apply to the dedicated process.

Basically, FPGAs and PSoC always involve some extra overhead for the flexibility. The overhead may diminish more and more, but as things scale up those small overheads become large ones. TANSTAAFL

Re:FPGA is nice but not a magic bullet. (2)

blair1q (305137) | about 3 years ago | (#35835414)

No, you're not doing any funky RF on-chip, unless someone is making specialized FPGAs with the RF goodies baked-in.

FPGAs are wizard for dev cycles, though, if your changes are only in the logical realm. No need to turn new boards; just reprogram the FPGA and get on with your life.

This guy's real problem is it's going to be as little as 1/N as fast as the N times bigger circuit he's replacing.

Re:FPGA is nice but not a magic bullet. (1)

jimmydevice (699057) | about 3 years ago | (#35837770)

FYI, Direct conversion of RF without a IF or tuning is where it's at today. Lousy selection though
Welcome to 2011

Re:FPGA is nice but not a magic bullet. (0)

Anonymous Coward | about 3 years ago | (#35835678)

They sound like they're takling about a more or less conventiinal SRAM based FPGA with fast bank switching. So a conventional FPGA, with suitable DAC/ADC, modulator, and other RF components could do Bluetooth or WiFi, but not really at the same time. This one could maybe run Bluetooth and WiFi on a practical time slice basis.

Re:FPGA is nice but not a magic bullet. (0)

Anonymous Coward | about 3 years ago | (#35836722)

I'd like to see an FPGA used as a GPU in a netbook or ipaq. If implemented properly (programmable by end developers) with dedicated ram for a framebuffer, it could blow away any single chip GPU for movie playback, and probably for gaming, too.

Because it'd be touched by end developers, and mimicked by competitors, its interface would need to be very standardized. Programmers need to know the size of the FPGA and have a means of dynamically sizing their code to it. Other things would have to be abstracted, since the wiring and interconnection is decided beforehand and would be different for every implementation.

Re:FPGA is nice but not a magic bullet. (0)

Anonymous Coward | about 3 years ago | (#35838284)

I'd like to see an FPGA used as a GPU in a netbook or ipaq. If implemented properly (programmable by end developers) with dedicated ram for a framebuffer, it could blow away any single chip GPU for movie playback, and probably for gaming, too.

Because it'd be touched by end developers, and mimicked by competitors, its interface would need to be very standardized. Programmers need to know the size of the FPGA and have a means of dynamically sizing their code to it. Other things would have to be abstracted, since the wiring and interconnection is decided beforehand and would be different for every implementation.

No it couldn't. GPU's are pretty damn good already. GPU:s use almost all their hardware when they're rendering frames, so there's very little room for improvement by reconfiguring a soft GPU on the fly unless you can reconfigure and re-optimize the whole FPGA completely between each frame, or something crazy like that.

I mean it feels like you might potentially have a small chance to beat a GPU if you make a soft GPU that's optimized for rendering a specific scene with a specific set of rendering options. Maybe. But probably not.

Re:FPGA is nice but not a magic bullet. (2)

tibit (1762298) | about 3 years ago | (#35838872)

The FPGAs needed to replace even fairly lousy shipping discrete GPUs cost on the order of $10k each. To replace a decent middle-of-the-pack GPU with an FPGA, you'd need to spend on the order of $100k in chips just for one board. Never mind that the board would consume on the order of 1kW of power, and good luck if your board assembly house messes something up: you lose a house's worth of hardware. It'd probably cost a couple $k to get the board assembled!

Delay Lines (1)

georgewilliamherbert (211790) | about 3 years ago | (#35835248)

Mmmm.... 40+ years after going out of style as "Hopelessly Obsolete", Delay Lines return to the cutting edge.

Re:Delay Lines (2)

blair1q (305137) | about 3 years ago | (#35835352)

Erm, no. This is kind of the opposite of delay lines. It's more like a pipeline, where each segment of the pipe is actually the same piece of silicon real-estate.

Your data goes through the entire pipeline, getting munged just as a pipeline would at each step, and comes out just how you want it.

Problem is, with a pipeline I can have a different datum in each segment. With this, one datum has to go through all the steps before I can feed another datum into the pipeline.

The pipeline gives me an N:1 speedup due to, well, pipelining. This gives me a 1:N cost reduction vs. that pipeline, but at the cost of all that pipelined speedup.

Just take that 1.6 GHz and divide it by N and you get his data throughput rate vs. a pipelined processor with N stages and a 1.6 GHz clock.

And if the original design only had 1 stage, but it filled up N squares of silicon, and his chip only takes 1 square, now it takes N cycles just to do the work of that original design. Again, divide that 1.6 GHz by N and you get his effective data rate.

So it's cheaper to fabricate, about the same price to program, makes your boards a hair cheaper (smaller packaging we'd hope), but it makes your stuff run hyper-slow.

Cheap chips for cheap toys.

Next!

Re:Delay Lines (0)

Anonymous Coward | about 3 years ago | (#35838808)

Cheap chips for cheap toys.

And this is exactly the segment where FPGA's have not been usable before.

Re:Delay Lines (0)

Anonymous Coward | about 3 years ago | (#35838932)

Cheap chips for cheap toys is kind of misleading. These chips can still run at an effective data rate of 200MHz, only slightly less than conventional FPGAs and not out of the ballpark of a typical target rate for an FPGA design. Additionally, these chips are targeted to be somewhere around 1/10th the price of a comparatively sized FPGA. For a midsized FPGA market, this could be significant.

FPGA for shipping products? (1)

oldhack (1037484) | about 3 years ago | (#35835256)

I've got kicked out of school with an EE degree, gone into software business (yeah, I know), and never looked back.

Do they ship products, other than dev kits, with FPGA?

Re:FPGA for shipping products? (0)

Anonymous Coward | about 3 years ago | (#35835330)

Yup all the time, specially in enterprise level new type of hardware such as storage and such where price sensitivity is low.

Re:FPGA for shipping products? (4, Informative)

blair1q (305137) | about 3 years ago | (#35835374)

Yup. Especially write-once FPGAs.

Sometimes making an FPGA is cheaper than building an equivalent board. You can get preprogrammed cells for entire microprocessors now. And lots of other library cells. Build an entire custom computer into a single package, if you want.

It's not dirt-cheap, but it's easy, and saves an assload on inventory.

Re:FPGA for shipping products? (1)

JamesP (688957) | about 3 years ago | (#35838888)

I didn't know write-once FPGAs were much popular

Most products I've seen use either a serial EEPROM, flash or code (up)loaded from another processor on the board.

Re:FPGA for shipping products? (1)

Richard Dick Head (803293) | about 3 years ago | (#35842950)

If your only tool is a x86 motherboard, I guess everything looks like a flash BIOS?

In other words, you might want to stick your nose in some medical equipment before you judge the popularity of FPGA's...

Re:FPGA for shipping products? (1)

Anonymous Coward | about 3 years ago | (#35835456)

Sure, but only some market segments.

For example, FPGAs are never as power or area efficient as dedicated silicon gates, and area equates to manufacturing cost. This tends to mean that for volume consumer apps, a dedicated ASIC will win out in the end.

The flip side is that FPGAs are much quicker and cheaper to develop for than an ASIC, so for specialist applications or small markets, FPGA win out.

These days FPGAs are starting to include more and more hardened blocks such PCIe interfaces, flash controllers and more recently ARM cores. For some applications this makes a very compelling proposal.

But FPGA will never be as power or area efficient as dedicated silicon.

Re:FPGA for shipping products? (0)

Anonymous Coward | about 3 years ago | (#35841458)

But FPGA will never be as power or area efficient as dedicated silicon.

Depends on how you look at it. If you can actually leverage the reconfigurability of FPGAs, rhen they can be vastly more area efficient for a given application. Certainly if you have one hardware process, then the ASIC is more efficient, but if you have distinct modes where you actually load different configs from time to time, then FPGAs can become vastly more space efficient.

Examples may include communication equipment supporting numerous modes and coding.

Of course I'm not saying this disputes your first sentence... this is still a bit of a niche/speical application.

Re:FPGA for shipping products? (3, Informative)

mrmeval (662166) | about 3 years ago | (#35835486)

All of our product have some sort of reprogrammable logic. PLD , GAL , EPLD, CPLD , FPGA, and some the designers should have been shot for making.

Without it we would not be able to design a product and get it to market with any hope of turning a profit. It keeps engineering costs low allows us to make changes for regulatory requirements and allows end users to load new firmware and fix problems in the field.

Some of our products are niche and low volume and some of our products are very high volume and we're growing.

Re:FPGA for shipping products? (3, Interesting)

erice (13380) | about 3 years ago | (#35835498)

I've got kicked out of school with an EE degree, gone into software business (yeah, I know), and never looked back.

Do they ship products, other than dev kits, with FPGA?

All the time. They tend to be low volume items with high unit cost. Cisco has been a big consumer FPGAs forever. It's not even all that uncommon to find FPGA's in consumer electronics, though they tend to be very small parts used a glue logic.

Re:FPGA for shipping products? (0)

Anonymous Coward | about 3 years ago | (#35838740)

You can also use FPGA:s to relatively quickly probe the market for a new product. If the product is popular you can convert your HDL codebase and move on to an ASIC.

Re:FPGA for shipping products? (2)

imsabbel (611519) | about 3 years ago | (#35835688)

Many IO cards use FPGAs.

I have seen them in interferometer controllers, motor servo boards, fast multi-io cards, etc. Most of the stuff is low quantity, expensive stuff ($5000+ per item), so it seems like its easier to put in an FPGA than creating a new chip for a few 100/1000 copies...

Re:FPGA for shipping products? (3, Informative)

the_raptor (652941) | about 3 years ago | (#35836236)

Plenty of tools like oscilloscopes now use FPGA's. Low end FPGA's are a couple of dollars tops, which is cheaper then the purchase plus production costs for a bunch of discrete chips.

A lot of hobbyist producers make designs with those low end FPGA's because it can be cheaper to use one FPGA over a whole bunch of products rather then stocking equivalent discrete IC's (ie you can buy an FPGA in 1000 quantities and use it across 10 products).

Of course this new product is just a cheaper FPGA, and their marketing claims are bullshit. Consumer electronics producers do not want upgradeable or repairable electronics. They want to be in the "fashion" business like Apple and sell new "upgrades" every year.

Re:FPGA for shipping products? (0)

Anonymous Coward | about 3 years ago | (#35836312)

FWIW RME's soundcards use FPGA for DSP

Re:FPGA for shipping products? (1)

JoeMerchant (803320) | about 3 years ago | (#35836314)

Lots of dedicated video encoder/compressor boxes on the market, I haven't seen one yet that wasn't FPGA based.

midi synth (1)

j1m+5n0w (749199) | about 3 years ago | (#35836454)

I have an EMU Proteus 2000 midi synthesizer that happens to have an FPGA in it. (I can't remember off the top of my head if it was a Xilinx Spartan or an Altera Cyclone, but I think it was one of those.)

Functional Programming will love this (1)

KublaiKhan (522918) | about 3 years ago | (#35835294)

With proper implementation, you could build chips that essentially are functional programs with this, and swap between programs as required. Fans of Haskell would likely realize some interesting benefits.

Re:Functional Programming will love this (2)

gtall (79522) | about 3 years ago | (#35835604)

You can do that with FPGAs, just go through a defunctionalization step which spits out a FSM. See Bill Harrison's work at U. of Missouri.

Re:Functional Programming will love this (2)

blackC0pter (1013737) | about 3 years ago | (#35835640)

Xilinx already supports this. You can load multiple different .bit files (fully compiled FPGA file format) into flash and then just reprogram the FPGA as needed on the fly. Also, FPGAs are great for general glue logic and massive individual IO connections. They allow you to have very low level control over signals that is just not the same in a microprocessor. They will definitely not replace a microprocessor for general program flow but they give you much tighter control over signals and signal timing. Have the FPGA do the low level things then punt it to the processor.

Although, it would be very nice to have an FPGA that ran faster than ~400-500Mhz. High performance FPGAs really require super wide buses and routing that is a nightmare. A chip running at 3x the speed would mean my buses could be 1/3 the width to handle the same bandwidth. You'd be surprised at the end of the day just what percent of your chip is dedicated to routing and buffering between clock domains when you deal with multiple 128-256+bit buses.

They may be attacking the wrong castle (3, Interesting)

Anonymous Coward | about 3 years ago | (#35835362)

The real problem with FPGAs is the painfully byzantine tools you have to use to deal with them. The chips themselves are fine.

There is a lot of room for disruption in the programmable logic tools industry. If this company is smart, they will focus on workflow and toolchain innovations, rather than becoming too distracted by shiny silicon baubles. Shorten the edit-simulate-synthesize-test cycle and you will make a lot of people happy.

"FPGAs are very expensive because they are large pieces of silicon," says Teig, "and silicon [wafer] costs roughly $1 billion an acre."

Then again, you should never argue with a man who buys his ink by the gallon, or his wafers by the acre.

Re:They may be attacking the wrong castle (0)

Anonymous Coward | about 3 years ago | (#35836110)

Yeah, you would think Xilinx would take the Gillette approach: give away the razor, sell the blades. But they still charge for licenses for their dev tools (yay! paying them repeatedly to fix their own bugs and support their own chips!) Why they charge, I can't comprehend. It's NOT for quality, that's for sure. They should stick to silicon.

Re:They may be attacking the wrong castle (2)

artor3 (1344997) | about 3 years ago | (#35836170)

"FPGAs are very expensive because they are large pieces of silicon," says Teig, "and silicon [wafer] costs roughly $1 billion an acre."

Then again, you should never argue with a man who buys his ink by the gallon, or his wafers by the acre.

Especially when he's so incredibly wrong. Silicon costs more like $10 million per acre right now (I had to look up the conversion, it's a kinda weird unit). The reason FPGAs are expensive is because of all the crap you need to implant and deposit and remove in order to make that silicon into a chip. And then you have the added cost of testing every single transistor in the chip to make sure that no little dust particle floated by and ruined the chip. That's where the size really hurts you, because one tiny defect wastes a large chunk of your wafer (though at least in FPGAs you can sell a partially damaged chip at a lower price).

The silicon itself is only a small portion of the price.

Re:They may be attacking the wrong castle (2)

Macman408 (1308925) | about 3 years ago | (#35836412)

I think it's closer to $100 million per acre, not $10 million, but what do I know? (That's based on ~$8000 per 12-inch wafer, which is an estimate I saw a year or two ago. Of course, maybe this guy is only getting 10% yield, in which case he's essentially right - and there's plenty of chips that are that bad, at least early in the product and process lifetime...)

Re:They may be attacking the wrong castle (0)

Anonymous Coward | about 3 years ago | (#35841406)

a lot depends on the wafer size that you use to calculate costs. it may be cheaper to cover an acre in smaller wafers than in big ones, or vice versa. but going by prices on this website:

http://www.universitywafer.com/Wafers___Services/Silicon_Wafer/silicon_wafer.html

(which are arguably not even close to the price most fabs pay) it would seem that a 12" wafer is cheapest vs surface area.
12"=$0.66/in^2
4"=$0.80/in^2

so using these prices and a figure of 6.27264 x 10 to the 6th power in^2 per acre, i get a final price of $41,399,424,000.00 per acre.

as there's no way in heaven or hell to create a wafer that size, it's a lot cheaper if you just want to cover an acre edge to edge with wafers. that would be 43,560 * $0.66... $28,749.80.

so either way his figures are wrong.

i'll leave the mm conversions to the natives, original sizes are listed in inches, but probably manufactured in mm.

Re:They may be attacking the wrong castle (0)

Anonymous Coward | about 3 years ago | (#35839126)

People in the chip industry often just say "silicon" when they mean the final, fabricated chip.

NeoCad + DIY FPGA (3, Interesting)

femto (459605) | about 3 years ago | (#35836264)

The disruption you mention almost happened in the early 90's. NeoCAD [findarticles.com] produced a compete competing tool chain for Xilinx FPGAs, including the place and route, for the then state-of-the-art 4000 series. Their software was better than Xilinx's, including things like a graphical layout editor. Xilinx was having none of it and bought NeoCAD. Quite a few NeoCAD features made it into the Xilinx software, eventually. Soon after that Xlininx started publishing less information on their FPGA's interconnect networks, and there has never been another attempt at writing such software.

Personally, I think writing a clone of the Xilinx software, today, is the wrong thing to do. It would be less effort to design and manufacture an "open source" FPGA, and write the necessary software from scratch, than to reverse engineer Xilinx's place and route.

Re:NeoCad + DIY FPGA (1)

boombox (188790) | about 3 years ago | (#35838074)

I have been thinking about the same thing as of lately. Creating an open source FPGA with full tools: Synthesis, Place and Route, low level FPGA editor and more.

I was thinking as a start to make something similar to the old Spartan-1 type fpga in a newer process. The marked targeted would be in between the CPLD and the smallish fpga's. (100 luts to 1000 luts)

The reason for this is that CPLD's are simple to integrate on board (no non volatile storage, only one supply voltage) but for small fpga's you already need a seperate configuration device, 3 voltage outputs more stringent decoupling. CPLD's only have maximum of 256 3-lut capacity before they are not cost effective anymore.

What I am missing is a small simple FPGA that does not have all the features of the more modern devices but with a spartan-1 level device you can still build some pretty impressive stuff. The device has 4 global clocks, 4 input luts that are configurable as 1x16 SRAM (you could opt for 6 input lut's these days). No multipliers, ram blocks, clock managers. This would be more targeted as a microcontroller replacement if made sufficiently low power and made running with a wide voltage range. I would still opt for an external flash storage device to reduce the FPGA price and complexity but using a standard serial flash chip.

Reverse engineering FPGA's seems like a time consuming and error prone job to do and you would always be a few generations behind. Not really an option.

Re:They may be attacking the wrong castle (0)

Anonymous Coward | about 3 years ago | (#35836402)

The real problem with FPGAs is the painfully byzantine tools you have to use to deal with them

I'm curious, what do you find byzantine about them?

Re:They may be attacking the wrong castle (1)

jimmydevice (699057) | about 3 years ago | (#35837800)

I worked for a company that ignored the tool problem. You had to perform routing and timing in your head and with a CAD GUI. Not pretty.

Re:They may be attacking the wrong castle (0)

Anonymous Coward | about 3 years ago | (#35839010)

http://rapidsmith.sourceforge.net/doku.php

Some interesting work using pre-placed and routed blocks. The first build is still slow if you have a some unique IP, but subsequent PARs can be done in a matter of seconds.

I think Virginia Tech is also working on some similar tools.

Re:They may be attacking the wrong castle (1)

HateBreeder (656491) | about 3 years ago | (#35839670)

Checkout: http://www.maxeler.com/ [maxeler.com]

They've been getting some pretty crazy results. If i understand correctly, they've got a completely innovative workflow, tool-chain and abstraction. I think they've even created their own simulation tools that give you cycle-accurate results 1000x faster than modelsim.

I'll believe it when I see it (2)

sharp3 (1195261) | about 3 years ago | (#35835402)

No mention of how easy these things are to program. Timing constraints will be very tight, and what happens if clock skew carries signals across folds? Any success depends on how well the accompanying tools can implement the standard synthesis flow to support multiple levels.

Re:I'll believe it when I see it (1)

pavon (30274) | about 3 years ago | (#35835708)

what happens if clock skew carries signals across folds?

I assumed that data was registered between fold switches.

Re:I'll believe it when I see it (0)

Anonymous Coward | about 3 years ago | (#35839124)

The data is stored between fold switches in temporary registers normally, but my understanding is that they do allow calculations to proceed through multiple folds on some conditions. As for CAD software, it's essentially equivalent to existing FPGA CAD tools. You can't really see the difference.

Re:I'll believe it when I see it (1)

Anonymous Coward | about 3 years ago | (#35842000)

No, they had to do their own synthesis since the synthesis step has to be combined with the time domain place/route to work. This is one of the reasons they have burned through so much money. We've not been able to establish a single application that the Tabula technology improves. This is all smoke and mirrors.

And there are no FF's in the technology -- only latches. We have no idea how clock domain crossing is accomplished.

Transputer on a Chip?... (1)

Anonymous Coward | about 3 years ago | (#35835408)

To me, after reading the papers, it looks like they reinvented (or reimplemented) Transputer architecture, but in a single chip, and with a different API.

Re:Transputer on a Chip?... (1)

Anonymous Coward | about 3 years ago | (#35836520)

To me, after reading the papers, it looks like they reinvented (or reimplemented) Transputer architecture, but in a single chip, and with a different API.

Uh, no. I'm sorry, but you probably have no clue what FPGAs are if you think that. Possibly transputers too.

There is no "API". FPGAs aren't devices for executing software. They're giant arrays of lookup tables used to implement logic functions. If you have a 16-entry LUT indexed by 4 bits, you can program the LUT to implement any possible logic function on 4 input bits. If you've ever taken a digital logic course, they're nothing more than truth tables. These LUTs and a bunch of other hardware building blocks such as D flipflops are tied together with a giant programmable routing matrix.

The innovation these guys came up with is that instead of having one fixed pattern for each LUT in the device, it can rapidly flip between N different patterns, and therefore N different logic functions. This is supposed to let them achieve more effective logic capacity per square millimeter of die area.

Transputers were general purpose CPUs designed to be tied together in some kind of network (I don't recall the details). They looked nothing like FPGAs, and didn't do this kind of time-sliced trick.

silly numbers - (0)

Anonymous Coward | about 3 years ago | (#35835534)

"and silicon [wafer] costs roughly $1 billion an acre."

Ok, lets put that in real units. How about a 100mm2 = 1cm2 chip die.
Hmm, that works out to only $24.

Why on earth did they pick the silly number of $1B an acre? Is it just a stupid PR scare number.
Anyone ever heard of a chip that uses acre's as a die size?

Hello marketing department? (0)

Anonymous Coward | about 3 years ago | (#35835652)

"Obsolescence is the curse of electronics" ... Uhm, no it's how companies make money...

Why you want to reconfigure on the fly. (0)

Anonymous Coward | about 3 years ago | (#35835656)

Say you have an FPGA on your computing device.
You decide to watch a video stream,
ZAP... the correct decoder is now in your FPGA
you are decoding way faster than in software running on a generic CPU.
Done viewing that,... switch to encoding ...ZAP... again way faster...
Intel put custom logic in their new SoC to handle encoding/decoding,
but it takes up space and what is there is limited and not changing.
You can have just about any heavy CPU task offloaded to custom hardware (assuming it fits on the FPGA)
And when you're not using it, it shuts down saving power.

So why don't they build systems like this?

Re:Why you want to reconfigure on the fly. (1)

Lunix Nutcase (1092239) | about 3 years ago | (#35835662)

Because 99% of people buying computers would find that a huge hassle?

Re:Why you want to reconfigure on the fly. (0)

Anonymous Coward | about 3 years ago | (#35835726)

99% of people don't know how a computer works, as long as it works.
Why would it be a hassle?
Do i as a user really care if its dedicated HW , software or a FPGA?
I don't think so, i'm more concerned about
1-Does it work
2-Is it fast
3-Is it cheap (on power)

Re:Why you want to reconfigure on the fly. (1)

Alotau (714890) | about 3 years ago | (#35835784)

Is it a huge hassle to offload video rendering to your graphics card?

Re:Why you want to reconfigure on the fly. (0)

Anonymous Coward | about 3 years ago | (#35835868)

Works on a desktop (with the right card) but not on my tablet / phone

Re:Why you want to reconfigure on the fly. (2)

artor3 (1344997) | about 3 years ago | (#35836210)

Because FPGAs are very expensive. The top end ones cost more than people want to spend on their entire desktop, just for that one chip. Custom logic will always be cheaper, because it only gives you what you need.

Also, your idea of shutting it down to save power doesn't really help. All chips go to sleep when not in use, there's nothing special about FPGAs in that respect.

Re:Why you want to reconfigure on the fly. (1)

j1m+5n0w (749199) | about 3 years ago | (#35836544)

So why don't they build systems like this?

I think it's mostly a matter of the toolchain being different and very, very primitive. My impression of Verilog (from a few trivial experiments) is that it's the sort of language you might expect someone to design 40 years ago. Also, many idiom are different. Some things may be easier, but programmers tend to take for granted that they can make random memory accesses -- they don't expect to need to implement a memory controller to do so.

Amazing use of factors (4, Funny)

Alotau (714890) | about 3 years ago | (#35835744)

For those of you who missed TFA, here is a juicy tidbit:

Teig estimates that the footprint of a Tabula chip is less than a third of an equivalent FPGA, making it five times cheaper to make, while providing more than double the density of logic and roughly four times the performance.

That is 6X more impressive than any other use of factors in a sentence... ever.

steve teig's latest failwin (5, Interesting)

Anonymous Coward | about 3 years ago | (#35835880)

the guy behind Tabula is behind a number of "failwins" in the electronics industry - a fail in that the technology ended up being pointless and rejected by the market, but wins in that his companies were all bought out by suckers for quite a bit of $$$$

two examples:

- X initiative (use 45 degree routing on chips) - look at http://www.xinitiative.org now - 100% dead. look at it, and all the wonderful claims he (and his sucker followers) made in archive.org.

- Simplex solutions - built a large number of poor quality EDA tools (poor because they never got adopted and so never got the real bugs worked out and features required for real work) but looked very shiny, so were sold to cadence for a fairly large sum of money (relative to the low dev. cost). All but one of the simplex tools (now called cadence QRC) has been EOLd by cadence, and QRC will be thrown out just as soon as anyone cares enough to replace it with something better.

You can bet Tabula, if it succeeds at all, will be another failwin. It will be bought by one of Xilinx or Altera (the current FPGA duopoly), a couple of minor good ideas will be incorporated into future products and the overwhelming majority of the Tabula technology will be promptly forgotten. ...why? I hear you ask?

The reason is simple: Steve Teig has realized that "spamming" technology really does work (for him) - he has figured out that he can leave it up to much larger corporations to figure out, in their own sweet time, why 99% of his ideas sound great but are actually pointless, in the months and years after they are fooled into acquiring his techno-spam through an acquisition.

From one of his many online bios [c-eda.org]:

He holds over 220 patents. In 2002, he broke Thomas Edison’s record for the number of patents filed by an individual in a single year.

Enough said.

Re:steve teig's latest failwin (3, Interesting)

Anonymous Coward | about 3 years ago | (#35837408)

I am working in the EDA business, and based on the biography you provided, Steve Teig looks far from being a frauder.
You point at the 'large number of poor quality EDA tools' in Simplex (which I never used), but you certainly know that EVERY EDA tools (from Synopsys/Mentor/Cadence) have its LARGE set of bugs. Why? Because quality is driven by ASIC design companies, and those companies do not understand that putting pressure on tool prices is hurting overall quality. Anyway.

"in 1982, he invented compiled-code logic simulation and led the development of the first simulator based on that technology." If I understand this claim correctly, Teig invented the technology which is still currently used in Synopsys' VCS, the fastest HDL simulator of the industry.

Based on the rest of this bio, Teig looks smarter than most EDA's boaad members. Maybe you are just jealous?

Re:steve teig's latest failwin (1)

meza (414214) | about 3 years ago | (#35839404)

Wow thanks for bringing my attention to such an interesting and fascinating guy. From what you write he sounds like a truly brilliant engineer and businessman man. Of course only a tiny proportion of all products make the dominating and long lasting impact on the market that you seem to want, think the light bulb, printing press or the integrated circuit. However an even tinier amount of inventions ever make it to the market or generate any revenue at all! This guy has been able to do that over and over again!

Over 220 patents! Enough said indeed! Wow, when does he even have time to come up with all these ideas, yet alone file for patent, start companies and make money. Fantastic!

Better writeup (4, Informative)

ayvee (1125639) | about 3 years ago | (#35836012)

Link [eejournal.com] to a better writeup, one that doesn't attempt strained architectural analogies (ignore the first paragraph or three, but do look at the comments).

Anyone else remember Starbridge? (1)

ndogg (158021) | about 3 years ago | (#35836428)

I remember Starbridge [slashdot.org], and their audacious claims, and this company sounds like it's trying to accomplish something similar, but aren't being as audacious with their claims.

I do look forward to software reconfigurable hardware, but that does mean it brings a whole new meaning to the word "bricking."

It's basically the same as any other FPGA (5, Informative)

Macman408 (1308925) | about 3 years ago | (#35836488)

...but it has fast context switching built-in. And you can't control when the contexts switch, they always go in order (as they should, since they're all statically assigned, and are different parts of a single problem, rather than separate problems).

For those that don't know how FPGAs work, here's a basic crash course: they have lots of blocks, each one has a look-up table (say a 4-LUT; 4 inputs, 1 output). The LUT is basically a "read-only" RAM with 4 address bits (so 16 addressable locations), and one data bit. The RAM can be rewritten (this is what is done when they program an FPGA), but it's fairly slow. Tabula changes it up a bit so that each addressable location is 8 bits instead of 1 bit. Since transistors are basically free on an FPGA (they're wire-dominated), this doesn't cost much, and it means that they can time-share pieces of silicon for different purposes without the penalty of reprogramming the chip. Then, each cycle, it'll pick a different one of the 8 bits (though the address, or inputs to the 4-LUT, may be changing at the same time).

It's a fairly straightforward idea, though there's a fair amount of complexity added to the design tools.

However, it's not free. You now have lots of high-speed logic, which is probably using tons of power, and it's switching frequently, which is using tons more power, and even when it's not, it's probably fairly leaky, using even more power. Effectively, you have a 1.6 GHz chip, but to you it seems like it's only running at 200 MHz - but it can do ~8 times more processing per silicon area. You might also think of it as being similar to the Pentium 4 integer units; they ran at twice the clock speed of the rest of the chip, so it seemed like there were twice as many of them (so a single IU could do an add in the first half of a core clock cycle, and a subtract in the second, computing two instructions per cycle).

So this chip is basically trading latency for computing power. The more operations you need to do, the slower it will run, because it'll take more of their folds to implement your logic.

Re:It's basically the same as any other FPGA (1)

Creepy Crawler (680178) | about 3 years ago | (#35836936)

So it does nothing infinitely fast?

Sounds like a fair tradeoff.

Re:It's basically the same as any other FPGA (0)

Anonymous Coward | about 3 years ago | (#35842218)

With more complicated tools. In the cloud no less.

Re:It's basically the same as any other FPGA (1)

davFr (679391) | about 3 years ago | (#35837298)

200Mhz is still a very high frequency for logic mapped on an FPGA. user-compiled logic does not reach this frequency on, let's say, a Xilinx's Virtex 5.

If Tabula can provide the equivalent of 8 FPGA in a single circuit, it will be a huge win for system designer. Multi-FPGA systems have reduced performance because signals must be propagated between FPGAs, via a limited number of IO pads. A PCB integrating a single FPGA (rather than 8 FPGAs) would be cheaper to produce, more compact, while providing better performance.

I will buy!

Re:It's basically the same as any other FPGA (1)

epine (68316) | about 3 years ago | (#35840148)

That's not a bad overview, but you need to apply some intelligence to the power consumption figures.

A|G || B|H
-+- || -+-
C|E || D|F

hope you enjoyed the preview (1)

epine (68316) | about 3 years ago | (#35840364)

Now back to the original program. Some year fer fools day, /. needs to randomize Preview/Submit.

That's not a bad overview, but you need to apply some intelligence to the power consumption figures.


A|G || B|H
-+- || -+-
C|E || D|F

My first instinct is to set up the eight bit shift register as a pair of four element squares; one clocking on the rising edge, the other on the falling edge. A mux at the bottom selects from the left/right square on alternate cycles.

Your clock is 800MHz instead of 1.6GHz. The time vias probably need at least a full clock cycle (no path from one clock edge to the next edge in the opposite direction).

The four-element circular shift register (you have these by the gallon) is highly optimized. It probably doesn't cost you much to cycle patterns 0000 or 1111. Patterns 0111(x8) and 0011(x4) have two edge changes per cycle on the 800MHz clock. Pattern 0101(x2) has four edge changes per clock. The software might optimize layout and placement for fewer of these patterns.

That will beat an 8-way mux, I think, in total logic transitions.

The design gives you more logic operations per unit of silicon; leakage current for unit of performance should only improve.

On average, you're driving signals less distance, so maybe average capacitive load is partially ameliorated. For some applications, the computational density will permit meeting performance goals with more efficient logic trees.

On the other side of the coin, you're totally at the Merced of the synthesis tools. I think this Meta-trans concept is extremely cool. The main problem is that no one has yet invented a de-stealthing tool that actually works.

Everyone run for cover, we're being attacked by Ro'ula's. If I were Xilinx, that would be the code name for my competitive response.

DSP FPGA (1)

epine (68316) | about 3 years ago | (#35840598)

The only FPGA I've used in my own design was a Spartan DSP. Heinlein's magic box isn't going to do you much good implementing 18x18 Wallace trees or adding conventional compute cores.

It's optimized for a very high LUT/pin ratio, in a small, hot package, discounting macro blocks.

I was more enthusiastic about mixed signal ASIC technology [triadsemi.com] from Triad, but on my initial inquiry they haven't lowered the cost of full-custom analog ASICs at the low end. What they seem to offer is a fairly expensive, but far less risky proposition (if theory translates to practice) for medium complexity design.

I would have needed to Scotty our projected volumes to get a second response.

Re:It's basically the same as any other FPGA (0)

Anonymous Coward | about 3 years ago | (#35842096)

What you've described is actually optimistic. And you've underestimated the added complexity needed in the tools. We haven't been able to establish that we can reuse the 4 to 1 mux in the fold more than 2-2.5 times in any reasonable logic application. The 8x claim is felonious nonsense. So what you have is >1000x more complicated than a standard FPGA, uses much more power, is slower, and is relatively small. Bad, bad, bad, and bad.

Note that the Tabula literature claims a 'LUT structure' in the fold. It isn't and they don't tell you the structure of the fold. That has to be reverse engineered from the tool output. The 'Tools in the cloud' is another tip that this company is unserious.

PS -- Xilinx nor Altera are dumb enough to buy this sorry stuff. Amongst those of use that are FPGA/ASIC specialists, this discussion is a hoot.

I don't know (1)

bugs2squash (1132591) | about 3 years ago | (#35836608)

what kind of process they're using, I imagine it will be a 40nm process or some similar feature size. What if we all just concentrated on making cheap short run fabrication machines, maybe something that could make a 150nm feature-size on pre-sliced wafers. That way I could quickly print something up in-house. Maybe my design could have some re-programmability, but I can't see that being the biggest use for FPGAs. Even if post-shipping re-programmability is feasible, I doubt many FPGA designs actually use it in their lifetimes.

Power Consumption = Not Ready for Prime Time (1)

Trip6 (1184883) | about 3 years ago | (#35836826)

"The power consumption if these devices is relatively high, and likely too much for a device like a phone" Dead giveaway that this is a marketing story, not a real proven technological renovation.

Impressive funding (0)

Anonymous Coward | about 3 years ago | (#35837228)

That's some impressive funding, 108 millidollars - that's a whopping 10.8 cents!

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