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Help Build the World's First Community-Funded CPU ASIC

timothy posted more than 2 years ago | from the dude-hook-us-up dept.

Open Source 140

An anonymous reader writes "The 32-bit OpenRISC CPU has been available for many FPGAs and was turned into a commercial ASIC in 2003. Now, the OpenCores community is asking for donations to create a new ASIC with the OpenRISC CPU, ethernet, PCI, UART, USB and other peripherals. The goal is to be able to sell these ASICs at a low price to anyone who wants to build a cheap embedded system built completely on open source. The OpenRISC currently runs on Linux 2.6.37 and has ports of gcc 4.5.1 among other things."

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Free at last (5, Insightful)

olof_k (2093198) | more than 2 years ago | (#35985306)

This is a milestone in open source history. No more complaining about undocumented behaviour that causes drivers to crash. It's just to download the RTL code and see for yourself what is going on. If this catches on, the chances of building truly open systems greatly improves. Go OpenCores!

Isn't SPARC open source? (5, Interesting)

Anonymous Coward | more than 2 years ago | (#35985412)

http://www.opensparc.net/ [opensparc.net]

Re:Isn't SPARC open source? (1)

olof_k (2093198) | more than 2 years ago | (#35985446)

There are a number of open source CPU cores, most notably are probably Leon and opensparc. I'm not sure, however if the OpenSPARC has been turned into an ASIC.

Re:Isn't SPARC open source? (4, Funny)

TheRaven64 (641858) | more than 2 years ago | (#35985542)

There used to be a small company that produced the OpenSPARC chips. I can't remember what they were called - Star? Solar? Something like that. Anyway, they were bought by some database company a while ago, and they still make those chips.

Re:Isn't SPARC open source? (1)

julesh (229690) | more than 2 years ago | (#35985564)

There are a number of open source CPU cores, most notably are probably Leon and opensparc. I'm not sure, however if the OpenSPARC has been turned into an ASIC.

I'm pretty sure it has been. The design is more suited to that application than FPGA synthesis (it's quite large, compared to what you can fit on most affordable FPGAs). Synopsys's ASIC design software includes modules derived from it for reuse on users' circuits; I'd be surprised if nobody had actually implemented something they'd designed using it.

Re:Isn't SPARC open source? (1)

mr_mischief (456295) | more than 2 years ago | (#35986090)

Fujitsu what?

Re:Isn't SPARC open source? (2)

ppc_digger (961188) | more than 2 years ago | (#35986874)

Fujitsu never implemented OpenSPARC. They developed the SPARC64 themselves, and the UltraSPARCs in their machines are manufactured by Oracle.

Re:Isn't SPARC open source? (1)

mr_mischief (456295) | more than 3 years ago | (#35987736)

Snippets from Wikipedia:

SPARC International was intended to open the SPARC architecture to make a larger ecosystem for the design, which has been licensed to several manufacturers, including Texas Instruments, Atmel, Cypress Semiconductor, and Fujitsu. As a result of SPARC International, the SPARC architecture is fully open and non-proprietary.

In March 2006, the complete design of Sun Microsystems' UltraSPARC T1 microprocessor was released-in open-source form at OpenSPARC.net and named the OpenSPARC T1. In 2007, the design of Sun's UltraSPARC T2 microprocessor was also released in open-source form, as OpenSPARC T2; see OpenSPARC.net.
As of June 2009 the SPARC design was used by Fujitsu Laboratories Ltd. to create the processor product named Venus SPARC64 VIIIfx which is capable of 128 billion floating point operations per second (128 GFLOPs).

There have been three major revisions of the architecture. The first published revision was the 32-bit SPARC Version 7 (V7) in 1986. SPARC Version 8 (V8), an enhanced SPARC architecture definition, was released in 1990. The main differences between V7 and V8 were the addition of integer multiply and divide instructions, and an upgrade from 80-bit "extended precision" floating-point arithmetic to 128-bit "quad-precision" arithmetic. SPARC V8 served as the basis for IEEE Standard 1754-1994, an IEEE standard for a 32-bit microprocessor architecture.
SPARC Version 9, the 64-bit SPARC architecture, was released by SPARC International in 1993. It was developed by the SPARC Architecture Committee consisting of Amdahl Corporation, Fujitsu, ICL, LSI Logic, Matsushita, Phillips, Ross Technology, Sun Microsystems, and Texas Instruments.
In 2002, the SPARC Joint Programming Specification 1 (JPS1) was released by Fujitsu and Sun, describing processor functions which were identically implemented in the CPUs of both companies ("Commonality"). The first CPUs conforming to JPS1 were the UltraSPARC III by Sun and the SPARC64 V by Fujitsu. Functionalities which are not covered by JPS1 are documented for each processor in "Implementation Supplements".
In early 2006, Sun released an extended architecture specification, UltraSPARC Architecture 2005. This includes not only the non-privileged and most of the privileged portions of SPARC V9, but also all the architectural extensions (such as CMT, hyperprivileged, VIS 1, and VIS 2) present in Sun's UltraSPARC processors starting with the UltraSPARC T1 implementation. UltraSPARC Architecture 2005 includes Sun's standard extensions and remains compliant with the full SPARC V9 Level 1 specification.
In 2007, Sun released an updated specification, UltraSPARC Architecture 2007, to which the UltraSPARC T2 implementation complied.
The architecture has provided continuous application binary compatibility from the first SPARC V7 implementation in 1987 into the Sun UltraSPARC Architecture implementations.
Among various implementations of SPARC, Sun's SuperSPARC and UltraSPARC-I were very popular, and were used as reference systems for SPEC CPU95 and CPU2000 benchmarks. The 296 MHz UltraSPARC-II is the reference system for the SPEC CPU2006 benchmark.

Snippet from SPARC International:

SPARC Architecture License

$99.00 Administration fee
Available to anyone, royalty free, gives developers the right to design, manufacture and freely market components conforming to the SPARC Architecture. Contact: sparcinfo@sparc.org for architecture license.

Okay, so $99 for a royalty free license isn't exactly pure open source.

Re:Isn't SPARC open source? (2)

mr_mischief (456295) | more than 3 years ago | (#35987778)

Damnit.. didn't mean to hit submit yet...

The actual exact implementation of a particular SPARC might not be completely open, but they are all built against an open spec to be called "Sparc". That's a far cry from x86 or POWER.

Re:Isn't SPARC open source? (3, Funny)

Anonymous Coward | more than 2 years ago | (#35985478)

I found a link to "Download the only free 64-bit micro processors". How do I install that in my MoBo? I'm running Vista.

Re:Isn't SPARC open source? (1)

michelcolman (1208008) | more than 2 years ago | (#35985526)

Mod parent funny! (I hope...)

Re:Isn't SPARC open source? (0)

Anonymous Coward | more than 3 years ago | (#35987760)

What does the Device Stage show you when you plug the thing in you MoBo? Since I'm thinking Device Stage as the homepage for your hardware, it should contain the necessary information for .. Oh crap, you are using Vista. I can't help you.

Re:Isn't SPARC open source? (1)

DaMattster (977781) | more than 2 years ago | (#35987318)

This looks very cool but who makes a motherboard capable of the processor? It is one thing to have the processor but without a complete motherboard, it is just one expensive trinket.

Price? (2)

Compaqt (1758360) | more than 2 years ago | (#35985460)

I applaud the effort, and I hope it succeeds. The community ought to have its own hardware.

But I hope the prices are a little less than those of OpenMoko [openmoko.com] and friends (BeagleBoard, FreeRunner, etc.) have been.

Re:Price? (1)

olof_k (2093198) | more than 2 years ago | (#35985518)

The price will probably depend a lot on the fab method, but the goal is to make it cheap and available. The main difference between this and beagleboard/arduino/freerunner is that they are all closed source ASICs. This is both a philosophical difference (Yeah! It's open source) and a practical (I wonder why the CPU is acting strangely, Oh well, I just have to look at the source code)

Fix? (1, Flamebait)

poptones (653660) | more than 2 years ago | (#35986062)

Too bad that, because it's an ASIC, all you can do is LOOK at that source code then try to design your code around the problem.

I'm down with open source, but this seems fantastically stupid to me. I can buy a pretty powerful CPU from a host of manufacturers at some very good prices - less than the $25 donation they request on their page, in fact.

We want to provide an alternative to the profit-hunting semiconductor giants who only provide "cost efficient prices" to large multi-national companies...

This is bullshit. This is about an agenda, not about the economic reality of "competing."

Re:Fix? (2)

olof_k (2093198) | more than 2 years ago | (#35986180)

But looking at the code and create workarounds that you know are working is a big step from guessing. Also, it theoretically enables you to optimize things, when you can monitor every register and clock cycle. Don't think that is very usable in reality though, but who knows. You don't need to donate $25 by the way. One dollar is fine

Re:Fix? (1)

poptones (653660) | more than 2 years ago | (#35986566)

You can no more "monitor every clock cycle" with one of these than with any other. No more do you have to "guess" than with any other. Intel and AMD have both shipped chips with WELL DOCUMENTED bugs in them. Moreover, they shipped REPLACEMENT chips in many cases. Sure sounds like a "greedy corporation" to me. Think one of these socialistic corps will be able to afford that?

Re:Fix? (2)

olof_k (2093198) | more than 2 years ago | (#35986720)

Yes you can monitor every clock cycle. In a simulator, that is. Also, I'm well aware that most vendors ship good documentation, and of course, opencores can probably not afford to ship replacement chips if a bug is found after the chips have been manufactured. However, it's a known fact that we have problems with undocumented hardware on Linux. Being able to fully analyze not just the CPU, but also ethernet, PCI, USB and other peripherals should be a welcome addition for all those that are writing drivers or debugging a strange hardware behaviour. I have no comments on your last two sentences

Re:Fix? (2)

tftp (111690) | more than 2 years ago | (#35987498)

Being able to fully analyze not just the CPU, but also ethernet, PCI, USB and other peripherals should be a welcome addition for all those that are writing drivers or debugging a strange hardware behaviour.

I did my share of that in FPGAs (Xilinx EDK) and I don't want to even hear about it. You buy a COTS MCU, solder it, and it works. You have reference designs that work, and they are done by the vendor.

What you are talking about is a completely new can of fresh worms. Making a working ASIC is hard; if you want as few bugs as possible then it's even harder. A buggy ASIC with an open-source RTL is a disaster. Yes, you can simulate it if you are crazy enough, but it takes lots of effort, and you can't simulate an odd timing error that occurs only now and then. ModelSim is not that fast, and you need to write lots of testbenches. In the end you will invest a lot of time into this debugging, and nobody knows if you can actually find a workaround. Your competitor, who picked a closed source MCU, would be already selling his product while you are busy explaining to the management why exactly your pick of the MCU was not so good.

In other words, there is no practical reason to select this chip over any other - unless you fear that on some unfortunate date all supplies of commercial MCUs stop. This is not possible, too much in this world depends on little 8-, 16- and 32-bit embedded systems, and you can always build your own computer out of them and run Linux on it. Your freedom of computing will be preserved, unless some laws make that, like owning a debugger, a crime.

Re:Fix? (1)

olof_k (2093198) | more than 3 years ago | (#35987700)

Timing errors are always the hardest things to track down. Fortunately we are talking about a fully digital ASIC with one clock domain, except for the memory controller, and some other things I might have ignored. I recently finished a project where we converted a FPGA to an ASIC that had more than 180 clock domains. That, my friend, was hard.

The logic bugs are mostly tracked down in simulation, and on the FPGA prototypes. Remember that the openRISC CPU has been available for some time already, runs Linux 2.6.38 fine and is being used in the industry. The RTL is mostly done except for ASICification of some parts.

The fear of suppliers running out of MCUs is real, I can tell you. Reverse-engineering of chips, and reimplementation in FPGA happens all the time in the industry. It is expensive and time-consuming, so having the source code and constraints around is a big help.

Re:Price? (1)

Man On Pink Corner (1089867) | more than 2 years ago | (#35986248)

(I wonder why the CPU is acting strangely, Oh well, I just have to look at the source code)

And by "source code" you mean "data sheet" or "manual," right?

It's funny... just as nobody is better at finding compiler 'bugs' than a beginning C programmer, it sounds like nobody is better at finding CPU bugs than Slashdotters.

Re:Price? (1)

olof_k (2093198) | more than 2 years ago | (#35986464)

No, I mean isolating the problem and running the RTL code in a simulator.

Re:Price? (1)

zill (1690130) | more than 2 years ago | (#35986128)

But I hope the prices are a little less than those of OpenMoko [openmoko.com] and friends (BeagleBoard, FreeRunner, etc.) have been.

$150 for a system powerful enough to run desktop linux and you're still complaining it's too expansive?

Re:Price? (1)

QuantumLeaper (607189) | more than 2 years ago | (#35986952)

The system I am currently running Linux on, I pulled from the Trash. It even included a monitor, but no cable for the monitor. It a P4 3GHz, 512M with a 320G HD, the bonus was some music, but most of the was crappy Country music and I don't mean Country is crappy, just their chose in music. So yes, $150 is expensive.

Re:Free at last (0)

Anonymous Coward | more than 2 years ago | (#35985830)

You can buy a Milkymist One for this, we are shipping today.
http://www.milkymist.org

Re:Free at last (1)

nurb432 (527695) | more than 2 years ago | (#35985856)

You do know the difference between ASIC and FPGA, right?

The story is about ASIC, which isn't exactly trivial. Doing a FPGA implementation of OR1/2k is a non-event.

Re:Free at last (0)

Anonymous Coward | more than 2 years ago | (#35986804)

Sparc has been open since start when it comes to specifications, and the Verilog code has been open for many years.
Sparcs was made and designed by many companies in the past due to that but the competition from Sun was to hard.

Opencores is a private held swedish company today making money by ads and consultants, it is not a .org company like opencores once was and this was
a great ad!!

You cant make chips like that, this is a smart ad by them simple as that.

Re:Free at last (1)

olof_k (2093198) | more than 2 years ago | (#35986932)

Sparc has been open since start when it comes to specifications, and the Verilog code has been open for many years.

Yes, that is true, but this is an attempt to produce a complete open source SoC as an ASIC, not just the CPU.

Opencores is a private held swedish company today making money by ads and consultants, it is not a .org company like opencores once was and this was a great ad!!

I think you confuse things here. The opencores servers are paid for by ORSoC. Opencores itself is the same as it always has been. Kind of like a sourceforge for HDL code. The ASIC project is partially funded by ORSoC as you can see on the donations page.

You cant make chips like that

I don't understand what you mean by that? This is exactly what opencores is trying to do

Re:Free at last (2)

blair1q (305137) | more than 2 years ago | (#35987268)

Wait. Are you saying that just because it's open source, it's fully documented? ...

Pardon me while I pick up my lung.

Nice (-1)

Anonymous Coward | more than 2 years ago | (#35985332)

My niggas in the streets could use a cheaper beagleboard.

Ho;;a!!!

Re:Nice (0)

Anonymous Coward | more than 2 years ago | (#35985470)

That's racist. Please use the term "negroes" or "colored brothers".

Re:Nice (0)

Anonymous Coward | more than 2 years ago | (#35985568)

"Ho;;a" is a Klingon racial epithet? Good to know, I guess...

Re:Nice (0)

Anonymous Coward | more than 2 years ago | (#35985576)

Those too are racist. Please instead use "pigmentally runaway" or "fried chickenum watermelonus".

I'm holding out for a home chip fab kit (0)

Anonymous Coward | more than 2 years ago | (#35985426)

How else could I be sure that the chips they sell are compiled from the published source?

Re:I'm holding out for a home chip fab kit (2)

nurb432 (527695) | more than 2 years ago | (#35985652)

Then use a FPGA and program it yourself.

Runs on? (1)

bcmm (768152) | more than 2 years ago | (#35985428)

Pretty sure Linux runs on a CPU, rather than the other way around.

Re:Runs on? (2)

maxwell demon (590494) | more than 2 years ago | (#35985452)

Pretty sure Linux runs on a CPU, rather than the other way around.

Unless the CPU is emulated. Then it might run on Linux.

Re:Runs on? (1)

blair1q (305137) | more than 2 years ago | (#35987274)

If it's done in an ASIC, it's almost certainly got an HDL model that has been run on Linux.

A little outdated don't you think (1)

Billly Gates (198444) | more than 2 years ago | (#35985438)

Why can't the opensource community build a more up to date one that is 64-bit with built in GPU. That would be nice for tablets

Re:A little outdated don't you think (1)

olof_k (2093198) | more than 2 years ago | (#35985486)

The OpenRISC spec supports 64-bit, but the current implementation is 32 bit. I agree with the GPU part. There is a cool project that has built a FPGA-based graphics card http://wiki.opengraphics.org/ [opengraphics.org] . One problem with the open source hardware community is that it is a bit fragmented. Would be awesome to combine a lot of the efforts.

Re:A little outdated don't you think (0)

Anonymous Coward | more than 2 years ago | (#35985514)

The open source community, in general, is a bit fragmented. KOffice, Abi, Open/Libre/whatever the fuckOffice

Re:A little outdated don't you think (0)

Anonymous Coward | more than 2 years ago | (#35986192)

www.ohwr.org is another effort to bring open hardware projects together

Re:A little outdated don't you think (1)

Anonymous Coward | more than 2 years ago | (#35985490)

If you hand 20-year monopolies to people like candy, then anyone else building something similar will be illegal or 20 years behind.

Re:A little outdated don't you think (0)

Anonymous Coward | more than 2 years ago | (#35985598)

Well, answer me this: why can't you build a more up to date one that is 64-bit with built-in GPU?

Re:A little outdated don't you think (1)

AdamHaun (43173) | more than 2 years ago | (#35985656)

This looks like an embedded microcontroller, in which case 32-bit is already very high-end. You realize all that Arduino stuff is based on an 8-bit CPU, right? Modern high-speed 64-bit CPUs are very difficult to design and expensive to fabricate.

Re:A little outdated don't you think (1)

inglorion_on_the_net (1965514) | more than 2 years ago | (#35985674)

Why can't the opensource community ...

It's not that we can't, we just haven't. Perhaps there isn't enough interest. Speaking for myself, I designed a CPU once, and concluded it wasn't for me. I'm a software guy.

If you want open source 64-bit CPUs with built-in GPUs, by all means go and start the project. It will work if the necessary effort is put in, and it won't have to be all your effort if you can motivate others to help out.

Re:A little outdated don't you think (1)

olof_k (2093198) | more than 2 years ago | (#35986198)

There is also the problem that for every hardware designer, there are probably more than a hundred software designers. There are so much stuff we would like to do, but there isn't enough time

Re:A little outdated don't you think (1)

Svartalf (2997) | more than 2 years ago | (#35987284)

The CPU's not really the hard part... The GPU is...

GNU Electric (2)

Script Cat (832717) | more than 2 years ago | (#35985456)

GNU electric is used to design ASICs. You need a good set of standard cells and a synthesis tool. Then you write the logic in VHDL or verilog.

OK, I'll Say It (1)

mprinkey (1434) | more than 2 years ago | (#35985496)

This is stupid.

I am a big proponent of open-source software. I like the idea of being able to build my own versions of software, fixing bugs and adding features. I use it as a key component of my business. It is great. Moreover, most of the code that me or my employees write is or likely one day will be open source.

However...open hardware is a fundamentally different thing. No one has chip fabs in their basement. So someone will have to pay big money to make the masks and tape-out and test the hardware. Unless some major vendor picks up the design and mass produces it lots of 100s of thousands, the price per CPU is going to be stupidly more expensive than an off-the-shelf CPU/motherboard or embedded system. And, even then, you are probably buying an overpriced, underpowered CPU just because it is "free."

This is Stallmanism as its worst--"freedom" for freedom's sake without regard to functionality or practicality. Stuff like this casts a shadow of crazy.

Re:OK, I'll Say It (4, Informative)

Bryan3000000 (1356999) | more than 2 years ago | (#35985556)

You don't understand. Chip fabricators will fabricate custom designed chips. Many companies have this done. Apple used to do it until they brought it in-house, and they still do for many components. If the design is actually completed and manufacturable, the only limit on price is the quantity of the order. This project can actually do what it intends.

Re:OK, I'll Say It (1)

mr_mischief (456295) | more than 2 years ago | (#35986124)

AMD used to fab chips, and sent some work to TSMC or IBM. Now they've spun off Global Foundries and still use TSMC.

So, yeah, I see your point about companies doing custom fabs for other companies.

Re:OK, I'll Say It (0)

Anonymous Coward | more than 2 years ago | (#35986786)

Is the chip truly open if it is made in a proprietary fab?

We need 'open' fabs too!

Re:OK, I'll Say It (1)

FlyingGuy (989135) | more than 2 years ago | (#35986826)

Sorry, that's a dumb question even for /.

Re:OK, I'll Say It (3, Informative)

Anonymous Coward | more than 2 years ago | (#35986894)

No, you don't understand.

From the GP:

No one has chip fabs in their basement. So someone will have to pay big money to make the masks and tape-out and test the hardware. Unless some major vendor picks up the design and mass produces it lots of 100s of thousands, the price per CPU is going to be stupidly more expensive than an off-the-shelf CPU/motherboard or embedded system. And, even then, you are probably buying an overpriced, underpowered CPU just because it is "free."

Repeat this until reality sinks in. He's not saying that chip fabricators won't fabricate custom chips. He's saying that the cost of getting them to do so is prohibitive. If your order volume is small, the fixed costs will eat you alive.

As for the project doing what it intends... the mission statement on the beg-for-donations page linked up above is full of monumentally dumb claims about how this is could revolutionize the industry and make the multinational giants quake in their boots. Yeah, right. The "multinational giants" and even the smaller players are busy working on chips which have reasonable technical specs for 2011 and beyond. These guys are making a trailing-edge toy which will have little appeal outside the niche of "people who must have everything in their computing lives approved by RMS".

Allow me to support that assertion. I've looked at the "detailed" technical plan, which is anything but detailed. There is a block level view of what's going in, which is mostly off-the-shelf OpenCores cores, but there are no detailed plans about how this is going to be translated into an actual ASIC design. There are only plans for making a FPGA based development platform.

Don't get me wrong, a FPGA platform is a good thing to do. A project like this won't have the resources to do very much design validation through simulation (which requires lots of people writing tests and running sims, i.e. real money), so FPGA based prototyping and validation is even more important than it is for conventional "closed source" ASIC projects. However, there is no plan given for how they're going to take their working FPGA design and turn it into an ASIC design. There isn't even any mention of which fab vendors and processes they're thinking of targeting. (and yes, these things matter immensely when you're making a chip.)

It's somewhat revealing that they're using a single small Altera Cyclone IV FPGA (under $60 qty 1 through Digikey). If you don't understand the significance, this means their design is tiny and trivial and low tech by current standards. The big boys they're planning to make quake in their boots need multiple ~$5K to $10K ea. FPGAs (big ones with well over 10x the resources of the FPGA the opencores guys are using) to fit all the logic in their upcoming System-on-Chip ASIC designs.

I suspect that if fully laid out their plan is something like "Build the FPGA version, and surely the ASIC guys will come knocking on our door with money to translate our awesome design into a chip!" But this will never happen, because their FPGA design is years behind the state of the art. They're competing against hordes of low cost chips which already do the same things and have already paid back their cost of development.

Re:OK, I'll Say It (1)

olof_k (2093198) | more than 2 years ago | (#35987154)

If your order volume is small, the fixed costs will eat you alive.

...which is why opencores is asking for donations

There is a block level view of what's going in, which is mostly off-the-shelf OpenCores cores, but there are no detailed plans about how this is going to be translated into an actual ASIC design.

1. Push ASIC button

2. Profit

Just kidding :) The CPU itself has been turned into ASICs before, so most of the code is in a good shape. The rest is implementation details and will probably be worked out when the ASIC vendor is chosen.

There are only plans for making a FPGA based development platform.

Don't get me wrong, a FPGA platform is a good thing to do. A project like this won't have the resources to do very much design validation through simulation (which requires lots of people writing tests and running sims, i.e. real money), so FPGA based prototyping and validation is even more important than it is for conventional "closed source" ASIC projects. However, there is no plan given for how they're going to take their working FPGA design and turn it into an ASIC design.

Verification is always the largest issue when you are building complex systems. One of the benefits of open source however, is that someone might have done it before you. In the case of the OpenRISC CPU, the 80000 (correct me if I'm wrong) regression tests of GCC is being used as one source of verification stimuli. Keep in mind also that the design isn't being created from scratch. The core is about ten years old

It's somewhat revealing that they're using a single small Altera Cyclone IV FPGA (under $60 qty 1 through Digikey). If you don't understand the significance, this means their design is tiny and trivial and low tech by current standards.

This isn't an effort to create the next-generation-273-bit-mega-hyper-threaded-with-DDR-5-and-379-core-subpixel-shader-gpgpu on crack. It's a fairly standard 32 bit RISC SoC, with the main difference that the RTL code is open source, and that the ASIC will be sold at a low cost even in low quantities. Think of how popular the Arduino platform is for example. It has some extra street cred, because the layout is open source. Now this is taken one step further, by using a LGPL:d CPU and peripherals. The quaking-in-their-boots part sounds a bit exaggerated, but still, it is primarily because this hasn't been done before. And if it turns out good, there is an ASIC proven SoC that can be modified and recreated by anyone that doesn't want to pay an ARM or a MIPS license for a 32-bit RISC system. Also, by using a fairly cheap FPGA, a reference board with either the ASIC or the FPGA can be sold at a reasonable cost.

Re:OK, I'll Say It (0)

Anonymous Coward | more than 3 years ago | (#35987958)

Yeah . I hear that open source thing will never work either.

Good call

Re:OK, I'll Say It (2)

artor3 (1344997) | more than 2 years ago | (#35987064)

Unfortunately, this project doesn't look to be completed or manufacturable. In fact, it looks like all they have is some HDL. Do they know what process technology they're going to use? Have they done any layout work? Did they do so with manufacturability in mind? Have they given thought to test modes? Do they have anyone to develop a test program?

Making a chip is hard. Even if you have all the IP, you're still looking at hundreds of thousands of dollars to develop a thorough test program and work out all the chip's kinks. Sure, you can just hand over the mask set to a foundry and buy the wafers, but then you have thousands of chips and no way of knowing which ones work, or how well.

Re:OK, I'll Say It (1)

Tapewolf (1639955) | more than 2 years ago | (#35985558)

However...open hardware is a fundamentally different thing. No one has chip fabs in their basement. So someone will have to pay big money to make the masks and tape-out and test the hardware. Unless some major vendor picks up the design and mass produces it lots of 100s of thousands, the price per CPU is going to be stupidly more expensive than an off-the-shelf CPU/motherboard or embedded system.

I remember reading somewhere about companies that will actually do short runs of chips for you. Memory is hazy, but IIRC it's typically done on a process several generations behind using older equipment that would probably be idle otherwise. I think what they do is stick different customers' parts on the same wafer or something like that... Wish I could remember where I heard about it.

Re:OK, I'll Say It (2)

AdamHaun (43173) | more than 2 years ago | (#35985638)

I think you're talking about MOSIS.

http://www.mosis.com/ [mosis.com]

Re:OK, I'll Say It (1)

blair1q (305137) | more than 2 years ago | (#35987298)

Huh. They've got TSMC 40 nm runs scheduled.

Build the right toy, and you could compete with the bigs on that.

Re:OK, I'll Say It (1)

Bengie (1121981) | more than 2 years ago | (#35986134)

Intel is leasing out 22nm fabs for FPGAs.

Re:OK, I'll Say It (0)

Anonymous Coward | more than 2 years ago | (#35985570)

Is that you Bill Gates?

Re:OK, I'll Say It (2)

olof_k (2093198) | more than 2 years ago | (#35985572)

No one has chip fabs in their basement. So someone will have to pay big money to make the masks and tape-out and test the hardware.

This is why opencores is asking for donations

Unless some major vendor picks up the design and mass produces it lots of 100s of thousands, the price per CPU is going to be stupidly more expensive than an off-the-shelf CPU/motherboard or embedded system.

Not necessarily. Of course, the more chips that are produced, the cheaper they get, but this is also a non-profit effort, so if you are looking to buy low quantities, it might be cheaper than commercial offerings

Re:OK, I'll Say It (1)

Arlet (29997) | more than 2 years ago | (#35985958)

Commercial 32 bit CPU chips are also very cheap. There's plenty of choice in the sub-$10 price range. Since every user a different requirements, it's hard to make an open source ASIC that they all want in sufficient quantities.

And who will guarantee the design will be continued after the first batch ?

Re:OK, I'll Say It (1)

TheRaven64 (641858) | more than 2 years ago | (#35986218)

And who will guarantee the design will be continued after the first batch ?

That's part of the point of an open source chip - and the reason that Sun open sourced the T1 and T2 designs. If you have a product that's built around this chip, then you can always get more, as long as there remain companies with fabs that produce chips from their customers' designs. You're never in the position of NASA, having to hunt for second-hand 8086s because they aren't produced anymore and the original supplier isn't interested in doing a low-volume run. They may be expensive, but they won't be unavailable. The time when it's not economically feasible to stick with the architecture is decided by you, not the supplier.

Re:OK, I'll Say It (1)

Arlet (29997) | more than 2 years ago | (#35986290)

Sure, you can always get more, but they may be very expensive, if you need only small quantities.

Re:OK, I'll Say It (2)

olof_k (2093198) | more than 2 years ago | (#35986482)

Yes, it might be expensive to manufacture small quantities, but availability is the key here. The space industry has learned it's lesson, and that's why they are interested in open source CPUs like LEON and OpenRISC

Re:OK, I'll Say It (1)

TheRaven64 (641858) | more than 2 years ago | (#35986734)

Less expensive than you might think. You can do small runs for around $10K (last time I looked was a few years ago, prices may have changed since then), and that's typically far less than the cost of rewriting your software stack for a new architecture and testing it for regressions.

Re:OK, I'll Say It (1)

TheRaven64 (641858) | more than 2 years ago | (#35985592)

Depends on the process. If you're happy with something a few generations out of date, it can be relatively cheap. I looked at it a few years ago with regard to the OpenSPARC stuff, and there were companies that would produce small runs surprisingly cheaply. You only need around 100-1000 for the per unit price to be expensive, rather than unaffordable.

The most important use, however, is companies wanting to produce their own SoC. Typically, they'll license a core from ARM, add some other things specific to their requirements, and then get it fabbed. Doing this with OpenRISC will cost as much to produce, but they don't have to pay ARM for the license.

Re:OK, I'll Say It (0)

Anonymous Coward | more than 2 years ago | (#35985624)

... most of the code that me or my employees write...

You wouldn't write "most of the code that me write". It is also customary to put others before yourself in a list.

... most of the code that my employees and I write...

Besides, open source hardware does make sense for large (but relatively small) manufacturers. There are small niches where an open source commons can result in price savings, even in hardware.

Re:OK, I'll Say It (1)

NEDHead (1651195) | more than 2 years ago | (#35985628)

I call for an open source project to provide low cost state of the art home chip fabs. That should solve the problem.

its not stupid (1)

nurb432 (527695) | more than 2 years ago | (#35985668)

You can do this in your basement with an FPGA on a slower scale, and i am sure that if enough orders were batched we could get a chip fab in some other country to make a 'smallish run' at a more reasonable cost than your estimate.. ( no, not 'cheap' but i don't think 100's of thousands either )

And 'free', or 'low cost' isn't the only selling point here, to me at least. 'Fully documented' and 'non-proprietary' is nothing to sneeze at.

Re:OK, I'll Say It (1)

TeknoHog (164938) | more than 2 years ago | (#35985846)

However...open hardware is a fundamentally different thing. No one has chip fabs in their basement.

And the reason is that FPGAs are cheap and much more fun.

Re:OK, I'll Say It (1)

mr_mischief (456295) | more than 2 years ago | (#35986138)

FPGAs are cheap in smaller quantities. Once you scale up ASIC production the per-unit cost falls well below FPGA chips and they're much faster.

Re:OK, I'll Say It (1)

TeknoHog (164938) | more than 2 years ago | (#35986200)

True, but my point was that open hardware designs are interesting since you can use FPGAs to play with them. I am personally excited by the possibilities of trying out different designs on my own desktop. The hardware may be slower, but it won't take ages and millions to get a working prototype.

Re:OK, I'll Say It (2)

mr_mischief (456295) | more than 2 years ago | (#35986298)

The key word is prototype. Once you have chosen the prototype, you can go to production with it. That's what this project is about. They are trying to find enough people who want this prototype that has been in FPGAs for a long time to go to larger-scale production with a higher speed chip as a result. Keep using FPGAs to figure out the core you want (or to play with as many as you want), but if you decide to put it into a mass-market item, an ASIC is probably the way to go.

Re:OK, I'll Say It (1)

gratuitous_arp (1650741) | more than 2 years ago | (#35987266)

This is stupid.

Troll much?

You're interested in what having source code can do for your business. The OpenCores community is interested in having free hardware. These are two very different interests. People who have different interests than you are not stupid. If you're old enough to talk about your business, you're old enough to grow up and realize that you don't have it all figured out.

This is Stallmanism as its worst--"freedom" for freedom's sake without regard to functionality or practicality

All I will say about this is it is rather shocking to hear this statement being cast in a negative light.

Re:OK, I'll Say It (1)

blair1q (305137) | more than 2 years ago | (#35987280)

Two words:

FP
GA

Who needs ASIC?

Open Source design tools? (1)

imadork (226897) | more than 2 years ago | (#35985596)

What is the current state of Open Source ASIC Synthesis and Layout tools? It does nobody any good to have an open RTL core if you need to pay the Synopsys tax (on top of the foundry NRE) to implement it.

Re:Open Source design tools? (1)

olof_k (2093198) | more than 2 years ago | (#35985634)

It is a bit thin on the ASIC side, but the simulation and development tools are picking up speed. Verilator [veripool.org] and Icarus verilog [icarus.com] are cool projects. Icarus can also do a bit of synthesis nowadays

Re:Open Source design tools? (1)

imadork (226897) | more than 2 years ago | (#35986460)

Seems to me you'd be better off implementing your Open-Source Hardware as FPGA's, anyway. You can get a lot of logic for a reasonable price, and the vendors are giving away the design tools for the cheap parts for free.

Re:Open Source design tools? (1)

nurb432 (527695) | more than 2 years ago | (#35985712)

I cant remember the exact name but some 15 years ago there was a functional open project for doing die design.. Not sure if its around anymore or not...

"sea or something" or other ...

My dream is a free SPARC T2! (1)

cpghost (719344) | more than 2 years ago | (#35985610)

Frankly, I'd love to buy one of those SPARC T2 chips, and since their design is already released under the GPL, it would be great to have an initiative to actually build them, so we can put them in desktops and laptops. Right now, they're tucked away in Oracle / Fujitsu (super expensive!) server-only land.

Re:My dream is a free SPARC T2! (1, Informative)

the linux geek (799780) | more than 2 years ago | (#35986164)

You don't want a SPARC T2, T3, or any other recent SPARC design in your desktop or laptop. Performance of a T3 is, accoridng to SPEC, very similar to a hugely cheaper and less power-hungry AMD Magny-Cours for massive-threaded applications... and much, much worse for few-thread apps. The "high-end" Fujitsu SPARC64 VII+ is also pretty damn slow.

Re:My dream is a free SPARC T2! (1)

cpghost (719344) | more than 2 years ago | (#35987486)

Well, I actually want it for simulations, because FPops are pretty good on a SPARC, and not every workload in this area is vectorizable on a GPU via OpenCL. Furthermore, SPARC is still a vastly superior architecture w.r.t. register windows and very fast thread switching. In my experience (purely subjective, I agree), even a lowly sun4u UltraSPARC IIIcu @1.5GHz still beats most high end Intel/AMD at nearly double that frequency for most day to day applications too. My only gripe with the Ultras is, of course, the lack of multiple cores, so that compiling can be pretty slow. So I hope that a multicore T2+/T3 would be at least on par with recent x86-ers even for normal uses.

Nice idea, but many pitfalls... (3, Insightful)

StandardCell (589682) | more than 2 years ago | (#35985644)

This is a nice idea, but there are a few serious problems with it:

1. If this doesn't catch on and people want it to continue, this could be a significant ongoing cost for running this project above and beyond allocating what people might think are one-time NRE charges. None of this appears to be detailed enough on that site so I'm not sure how far they've thought through this. Who are the target vendors, and have they tendered bids? Costs vary greatly, and I'm not at all ready to throw money when there appears not to be an "open source" plan with sufficient detail to make this real, nor with open listing of the credentials of the individuals involved. If you're gathering up to $250k for a project and you want my money, I had damned well better know that you're able to execute and that you have a real plan and definitely not just an FAQ.

2. How did they define the product? Is it based on market needs? If so, what markets and where is the information on said markets? If it's for hobbyists, I get that, but did anyone do even a rudimentary survey to say how many timers or UARTs might be necessary, whether they should embed an MMU so you can run a more advanced OS, or what the max CPU clock speed should be? If *I* am going to put my money in it, then why not ask *me* what I want? And yeah, I know I can contribute, but how have all of those contributions been managed, organized and synthesized into what is being built AND make it sufficiently relevant for enough time that this would be worth doing before technology moves on? I don't see a single place for that around their site.

3. Frankly, why bother when there are many other vendors such as Microchip who offer 32-bit micros with fully-documented architectures and better capabilities that you can run Linux on? I know, I know, this is what open source is about, but we're not just talking about someone's spare time on a machine they do other things with; this is a real product with real implications. I seriously don't buy how they're going to change the industry since the successful players in the industry guarantee supply to their customers.

I know I'm going to get flamed and down-voted for this post, but the open source hardware world is much tougher than the software world, and ASIC designs are steadily dropping because ASSPs are taking their place. I think people's efforts need to be focused on software, and this is coming from a guy who's been on Slashdot more than a decade with a hardware background (and hence my name) and has switched to the software and systems world...

Re:Nice idea, but many pitfalls... (2)

olof_k (2093198) | more than 2 years ago | (#35986448)

I understand your critisism, and I also would like to see a more detailed plan. Since this is a pilot project, some things will have to be worked out during the planning phase.

1. If this doesn't catch on and people want it to continue, this could be a significant ongoing cost for running this project above and beyond allocating what people might think are one-time NRE charges. None of this appears to be detailed enough on that site so I'm not sure how far they've thought through this. Who are the target vendors, and have they tendered bids? Costs vary greatly, and I'm not at all ready to throw money when there appears not to be an "open source" plan with sufficient detail to make this real, nor with open listing of the credentials of the individuals involved. If you're gathering up to $250k for a project and you want my money, I had damned well better know that you're able to execute and that you have a real plan and definitely not just an FAQ.

As it is stated in the FAQ, the more money donated, the smaller process opencores can afford. That will also decide the possible ASIC vendors that can be used. I'm a bit curious about what other costs than the NRE that you are thinking of

2. How did they define the product? Is it based on market needs? If so, what markets and where is the information on said markets? If it's for hobbyists, I get that, but did anyone do even a rudimentary survey to say how many timers or UARTs might be necessary, whether they should embed an MMU so you can run a more advanced OS, or what the max CPU clock speed should be? If *I* am going to put my money in it, then why not ask *me* what I want? And yeah, I know I can contribute, but how have all of those contributions been managed, organized and synthesized into what is being built AND make it sufficiently relevant for enough time that this would be worth doing before technology moves on? I don't see a single place for that around their site.

The OpenRISC has been used in many projects before. The IP cores that are going into the ASIC should cover most basic needs. There is also a PCI bus included to cover some additional uses. A MMU will most certainly be included, since it is targeted towards running standard Linux. The CPU speed will be limited by the process, and the current design. Still, I agree that there should be a place for these kinds of discussions. I'm guessing there will be one. For now, slashdot will have to do :)

3. Frankly, why bother when there are many other vendors such as Microchip who offer 32-bit micros with fully-documented architectures and better capabilities that you can run Linux on? I know, I know, this is what open source is about, but we're not just talking about someone's spare time on a machine they do other things with; this is a real product with real implications. I seriously don't buy how they're going to change the industry since the successful players in the industry guarantee supply to their customers.

I think there are a lot of use cases for this. You can buy these cheap ASICs and build a system. If you need to hardware accelerate something, then you can replace the ASIC with a FPGA and extend the design. Come to think of it, it seems kind of backwards to prototype on an ASIC and then implement it in a FPGA :)

I know I'm going to get flamed and down-voted for this post, but the open source hardware world is much tougher than the software world, and ASIC designs are steadily dropping because ASSPs are taking their place. I think people's efforts need to be focused on software, and this is coming from a guy who's been on Slashdot more than a decade with a hardware background (and hence my name) and has switched to the software and systems world...

I really hope that you are wrong here. Open source efforts should be able to handle as much criticism as other projects. Regarding your other point, what I see is that the borders between hardware and software are changing. Things that used to be done in ASIC is now done in software and the other way round. There are also many cool ideas how to decide what is going into hardware and software at compile time.

Re:Nice idea, but many pitfalls... (0)

Anonymous Coward | more than 3 years ago | (#35987926)

Another bit to consider is the patent implications. The big chip guys have been working on this sort of thing for a *VERY* long time and have a *VERY* long list of patents. HW manufactures are *REALLY* into patents it is how they protect themselves from each other and cross license things is usually the norm. Many of them are not afraid of court either. They live it and breath it.

I am not questioning whither it could be done the 'open source' way (as it could be). I am saying the road will be a very tough one legal wise.

Re:Nice idea, but many pitfalls... (0)

Anonymous Coward | more than 2 years ago | (#35986524)

I know I'm going to get flamed and down-voted for this post,

tl;dr, but I'm going to mod you "redundant" just for saying this!

Re:Nice idea, but many pitfalls... (1)

Kjella (173770) | more than 2 years ago | (#35986780)

I never got the allure of open hardware. Pretty much all the benefits from open source is that you can change it easily, but you'll never be able to make individual ASICs. If you want any change you'll have submit it to some committee that'll gather up changes for a production run, potentially rejecting yours and/or accepting others you don't want. You will never be in any real control of the hardware you run.

Many chips are extremely well documented how they function, sure they have bugs in errata lists but that's exactly because silicon bugs are expensive to fix. Also hardware is far less binary, like for example the Intel SATA bug they had - it passed all tests with the reviewers but the controller would stop working over time. What if you get a bug like that in your chip? There's no "patch and recompile" it's "throw away and buy another".

I'm sure RMS will buy one, but I can almost guarantee that I will not. But if there are enough people like RMS out there, feel free.

HDCaml (2)

inglorion_on_the_net (1965514) | more than 2 years ago | (#35985732)

Speaking of grassroots chip design, what is happening with HDCaml these days? I thought the idea was pretty neat when I first heard of it (a hardware design language that is nicer to work with than VHDL and Verilog!), but is anybody actually working with or on it? Or any other improvements on the established languages?

Re:HDCaml (3, Informative)

olof_k (2093198) | more than 2 years ago | (#35986130)

Haven't heard of HDCaml before, but the idea of inventing a nicer languange than Verilog and VHDL lives on. System Verilog adds a lot of syntactic sugar and new functionality, and there is a cool project called MyHDL that uses Python. System Verilog is gaining popularity in the industry, but unfortunately there aren't any open source tools to work with it yet. The commercial ones don't seem to implement the full language either. A bit like the HTML5 situation. We could really need something though. Even after having spent nearly ten yers doing hardware design, I find the two main languages horrible to work with.

Prices (2, Informative)

Anonymous Coward | more than 2 years ago | (#35986374)

I work for a company that produces outsourcing for ASIC supply chain. Assuming a 130nm process, we are talking about $750K for masks and the like and $250k for Non-recurring engineering. Manufacturing run requirements would be a half lot at 8 inch- 12 wafers at probably 100-150 units per wafer MINIMUM.So expect a production run of at least a thousand.

I don't think this project can be done on commercial terms.

MIPS (2)

BigFootApe (264256) | more than 2 years ago | (#35986714)

While poking around a couple of weeks ago, I found a couple of HDL sources for MIPS R3000 cores. Would these run into licensing issues? They could be adapted to something similar, or perhaps other uses with the addition of on chip I/O and perhaps a vector unit, IMHO.

Re:MIPS (2)

olof_k (2093198) | more than 2 years ago | (#35986754)

Not sure about MIPS, but ARM is quick to act if someone puts out ARM clones, and I guess the same principle would apply to MIPS clones, as they both are licensable. The difference is that the R3000 is from 1988 (according to wikipedia), which probably makes it less interesting

Re:MIPS (1)

Anonymous Coward | more than 3 years ago | (#35988090)

Can you give us a link for those R3000 cores, please?

Vaporware or pipe dream ? (1)

slincolne (1111555) | more than 2 years ago | (#35987392)

They don't appear to have an actual chip at the moment. From looking through their web site they have a design that can be downloaded to an FPGA, and a software simulator. That is a very long way from a real product.

Why would anyone think this is a viable idea for the open source community ?

Maybe if someone like AMD got behind it ?

Without a long term commitment from a reliable manufacturer to supply these at a competitive rate for 5+ years there is a large risk that people investing in designs using this chip will be left high and dry. They would be far better to look at some of the ARM derivatives where at least you are not locked into a boutique supplier. The only thing that could make this a useful idea would be the availability of FPGA chips at the same price point - not holding my breath there.

Orgasm. (1)

unity100 (970058) | more than 2 years ago | (#35987464)

Im >.
thank you, people.
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