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TSMC To Spend $10B Building Factory for 450mm Wafers

Soulskill posted more than 2 years ago | from the those-are-some-small-cookies dept.

Hardware 104

An anonymous reader writes "With demand for processors growing and costs rising, using larger wafers for manufacturing is highly desirable, but a very expensive transition to make. TSMC just announced it has received approval from the Taiwan government to build a new factory for 450mm wafers, with the total cost of the project expected to be between $8-10 billion. The move to larger wafers isn't without its risks, though. Building new facilities to handle production is the easy part. The industry as a whole has to overcome some major technical hurdles before 450mm becomes a viable replacement for the tried and tested 300mm process. TSMC's chairman Morris Chang has stated the next five years will be filled with technical challenges, suggesting 450mm wafers may not be viable until at least 2017."

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How about (3, Informative)

afidel (530433) | more than 2 years ago | (#40300523)

How about they focus on fixing their 28nm production problems before they set their eyes on lowering cost through bigger wafers. It's not like many of their most lucrative clients aren't hobbled at the moment by lack of supply for their top bin parts. Oh, yes they are.

Re:How about (1)

fiannaFailMan (702447) | more than 2 years ago | (#40300571)

How about they focus on fixing their 28nm production problems before they set their eyes on lowering cost through bigger wafers. It's not like many of their most lucrative clients aren't hobbled at the moment by lack of supply for their top bin parts. Oh, yes they are.

Apply for the CEO's job then.

How about getting the units right? (-1, Troll)

Forty Two Tenfold (1134125) | more than 2 years ago | (#40300721)

I know USAns are terrible at metric system, but skewing the prefix by 6 orders of magnitude is just plain stupid. To make it easier for you USAns it's 450nm or 177nin (nanoinches, not Nine Inch Nails).

Re:How about getting the units right? (-1, Offtopic)

Anonymous Coward | more than 2 years ago | (#40300751)

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Re:How about getting the units right? (0)

Anonymous Coward | more than 2 years ago | (#40303711)

So what you're saying is:

"A few weeks ago, [blah blah blah, bullshit bullshit bullshit]... use my product I'm pretending not to be a shill for..."

It is easy for an AC to post total bullshit and lies. Or perhaps their own marketing dept. wrote this. Since I won't follow a link in the post (never do that under these circumstances) I have no way of knowing for sure.

The real question is, how did it make it onto /.? Did someone figure out how to defeat the captcha, or was this done manually?

Re:How about getting the units right? (1)

ifiwereasculptor (1870574) | more than 2 years ago | (#40305715)

I'm a fan of your heartwarming tales, but this wasn't as good as some of your past work. My favorite is still the one where you get cancer and start abusing your daughter. Please, persevere on your fight, whatever it may be. Your fans have faith, and we are legion.

Re:How about getting the units right? (1)

Forty Two Tenfold (1134125) | more than 2 years ago | (#40300769)

...or 14.6ypc

Re:How about getting the units right? (0)

Anonymous Coward | more than 2 years ago | (#40300831)

Sorry, but you are the guy who's wrong. 450 nm technology is sooooo old...
RTFA

Re:How about getting the units right? (4, Informative)

Kjella (173770) | more than 2 years ago | (#40300851)

I'm sorry, but you're the one making a fool of yourself. The process is 28 nanometers, the wafers are now 300 millimeters wide and will be 450.

Re:How about getting the units right? (1)

Forty Two Tenfold (1134125) | more than 2 years ago | (#40300909)

Yes, and I RECANT.

Re:How about getting the units right? (0)

Anonymous Coward | more than 2 years ago | (#40301001)

Which do you recant: that one single post, or the blanket notion that "USAns" are idiots?

Re:How about getting the units right? (1)

Forty Two Tenfold (1134125) | more than 2 years ago | (#40305977)

Take a wild guess.

Re:How about getting the units right? (1, Informative)

Anonymous Coward | more than 2 years ago | (#40300885)

TSMC Chairman Morris Chang told reporters he expected other rivals such as Samsung were also working on developing a 450mm, or 18 inch, wafer.

"18-inch is something we have to do, but the technology is not ready yet ... if we can overcome it, it'll be a big breakthrough," he said after the company's annual general meeting.

I know Europers are bad at reading comprehension, but this isn't the precision of the wafer, it's the size. They're planning to make a lot more chips each run.

Re:How about getting the units right? (1)

Forty Two Tenfold (1134125) | more than 2 years ago | (#40305987)

Europers

It's Europeans, and how can you be sure you even hit the right CONTINENT?

Re:How about getting the units right? (1)

mwvdlee (775178) | more than 2 years ago | (#40300903)

450mm refers to wafer size (http://en.wikipedia.org/wiki/Wafer_(electronics)).
28nm refers to a fabrication process (http://en.wikipedia.org/wiki/Semiconductor_device_fabrication).
They're not off by 6 orders of magnitude, you are.

Re:How about getting the units right? (1)

jamiesan (715069) | more than 2 years ago | (#40308207)

When will they learn!? Size doesn't matter! It's all about the frequency!

The more it hertz the better!

Re:How about getting the units right? (0)

Anonymous Coward | more than 2 years ago | (#40300927)

How about getting the prefixes right?

Re:How about getting the units right? (1)

plalonde2 (527372) | more than 2 years ago | (#40301251)

Wafer diameter is in millimeters. Process feature size is in nanometers. No error was committed in prefixes.

Wafer handling is a big deal, and the bigger the wafer the less waste there is at the circumference, increasing yield.

Re:How about getting the units right? (1)

crbowman (7970) | more than 2 years ago | (#40301981)

Uh, no! They are correctly referring to 450mm *wafers*. 450 mm or about 17.7 inch diameter *wafers*. Not line width wafer diameter. This represents a roughly 125% increase in area over current 300mm wafers, and since the marginal cost of processing a 450mm wafer over a 300mm wafer is no where near 125% (it's mostly in the cost of the newer machinery) TSMC will be able to significantly decrease the cost of their products and so will companies like NVidia, ATI, Broadcom and Qualcomm (NOT Apple they don't make chips at TSMC yet). We Americans may not be great at using the SI system but at least we know what where talking about.

Re:How about getting the units right? (0)

Anonymous Coward | more than 2 years ago | (#40305943)

Some EU people are actually well versed in physics and understand things like the SI system. Pretty sure the average American ./ poster is equally confused.
So, I would suggest that we all adopt the convention of expressing diameters in inches and everything else in metric. With the exception of pounds/kg of thrust, this would be better expressed in libraries of congress at a specific moment in time. I hope the editors will take appropriate action for the next space related submissions.

Re:How about getting the units right? (1)

Forty Two Tenfold (1134125) | more than 2 years ago | (#40305965)

TSMC will be able to significantly decrease the cost of their products and so will companies like NVidia, ATI, Broadcom and Qualcomm (NOT Apple they don't make chips at TSMC yet)

COST vs PRICE.

We Americans

Are you talking on behalf of both continents?

we know what where talking about

WMDs in Iraq (BTW you can't even pronounce Iraq properly), Iran building nuclear weapons, cannabis being a "dangerous drug" on par with heroin, um... [job] creationism. No. If your "elite," creme de la creme looks that stupid, what can be said about the average? "Is your children learning?"

Re:How about getting the units right? (1)

CycleMan (638982) | more than 2 years ago | (#40305959)

I know USAns are terrible at metric system, but skewing the prefix by 6 orders of magnitude is just plain stupid. To make it easier for you USAns it's 450nm or 177nin (nanoinches, not Nine Inch Nails).

Incorrect. It is 450 millimeters (mm) in diameter. This translates to an approximately 18 inch diameter wafer. And that is huge. It needs completely new tools and materials handlers to be designed and tested; you can't just upsize the existing things, especially given the drive to decrease the thickness of wafers, thus increasing their fragility.

Re:How about (1)

Jeng (926980) | more than 2 years ago | (#40300627)

How about they build for tomorrow so they aren't stuck with yesterdays technology?

They can build new factories that will use new technologies at the same time that they are operating present factories working on perfecting current technologies. It is not a one or the other situation, it is best to do both.

Re:How about (1)

afidel (530433) | more than 2 years ago | (#40300699)

True, but I doubt there are that many good process engineers in the world and the ones TSMC employs really, really need to be focused on fixing their current process, not working on setting up the new factory (though I guess site prep probably takes a year or more so it's admittedly probably not an issue). I'm just personally annoyed that I'm still running a 3 year old GPU because the inexpensive low power parts aren't available because 100% of current production is going to the highest margin parts. I want a better passively cooled card than my 5750 but the next generation has been on hold for the last six months due to TSMC production issues.

Re:How about (1)

Jeng (926980) | more than 2 years ago | (#40300879)

Per the article it is going to take nearly five years for them to complete the factory and get it up and running.

Would you prefer for them to start now or later?

Btw, would this video card work for you?

http://www.newegg.com/Product/Product.aspx?Item=14-102-980&SortField=3&SummaryType=0&Pagesize=10&PurchaseMark=&SelectedRating=-1&VideoOnlyMark=False&VendorMark=&IsFeedbackTab=true&Keywords=(keywords)#scrollFullInfo [newegg.com]

Re:How about (1)

Tanktalus (794810) | more than 2 years ago | (#40301301)

Re:How about (2)

Anonymous Coward | more than 2 years ago | (#40301333)

Just don't install Linux on it, you won't be able to return it if it's defective.

never go full retard

Re:How about (1)

mwvdlee (775178) | more than 2 years ago | (#40300979)

There may not be many good process engineers in the world, but putting all of them on a single problem isn't going to fix that problem sooner.
Like nine women aren't going to give birth to a baby in one month.

Re:How about (4, Interesting)

Penguinisto (415985) | more than 2 years ago | (#40301037)

Small prob with that...

Intel recently built up (still building? can't recall) a new fab here in Oregon. It'll cost them $1bn or so, all said and done. Dropping that many ducats at a time gets expensive after awhile, even for a beast as big as Intel. Meanwhile, they still have a fab going that was originally built in the 1980's (the Aloha facility, if you're curious), and after they're done running whatever iteration they have passing through it now, it'll be useless as a fab (the walls are basically swiss cheese by now with all the holes punched and patched through them to accommodate new processes, new chip types, new machinery, etc).

Personally, I'm kind of curious how a 450mm wafer is going to do them much good.

Having worked in the solar industry (growing crystal is the same process as semiconductors for mono PV wafers), the CZ process [wikipedia.org] used to grow monocrystal wafers eats a lot of time, and you can only get so much weight hanging off the "seed" (starter crystal) before it breaks. There's also the fact that as diameter increases, the need for more precise control over rotational speed during the grow increases (the thing spins at a precise speed, slowly pulling the cylindrical crystal out of a molten vat). I guess what I'm getting at is, sure they can have something at 450mm with enough precision and effort, but the resulting crystal would also have to be shorter overall, if only to keep the weight from snapping the seed crystal (causing the thing to splash back into the vat, tearing the crucible up, making a mess, and oh yeah - ruining the multi-hour run).

Long story short, they can likely (with a lot of effort, not to mention newer/bigger machinery) get bigger-diameter crystals, but because the seed can only be so big, the wafer yield will likely drop significantly.

Re:How about (3, Funny)

ibsteve2u (1184603) | more than 2 years ago | (#40301161)

but the resulting crystal would also have to be shorter overall, if only to keep the weight from snapping the seed crystal (causing the thing to splash back into the vat, tearing the crucible up, making a mess, and oh yeah - ruining the multi-hour run)

No problem; Taiwan small island, less gravity. Care to invest?

Re:How about (1)

Anonymous Coward | more than 2 years ago | (#40301655)

You've explained why it's currently not being done. But I think it's safe to assume that TSMC knows all of this, and they obviously think they've found some viable solutions to the challenges you list. If so they gain a competitive advantage. The world is full of things that were at one point considered impossible/impractical/uneconomical. Proving otherwise is how tech advances.

Re:How about (2)

Savantissimo (893682) | more than 2 years ago | (#40301765)

Bigger wafers means less waste around the edges where the rectangular chips meet the circular wafer edge. This becomes very important for larger chips such as image sensors. (Not sure if the new process will be used for that, though.) Also, many manufacturing steps are applied to the wafer as a whole, and having wafers with over 2.25 times as many chips makes those steps cheaper on a per-chip basis. Making the boules will be hard, but I think they will find some way of providing extra support for the boule as it grows. Thinner wafers may also get more out of each boule. There will be many other problems such as maintaining alignment over the greater distance which may be harder.

Re:How about (1)

AussieNeil (1757216) | more than 2 years ago | (#40303165)

...Thinner wafers may also get more out of each boule...

Going to thinner wafers is very difficult as the wafers become more fragile and are also more likely to warp during processing.

Re:How about (1)

Penguinisto (415985) | more than 2 years ago | (#40304933)

Sorta.

They likely use the same wire-saws to carve 'em out that I saw in the solar industry - the biggest worry there is kerfing along the face of the wafer, making it harder to surface properly. Once you start getting too thin, it ain't warping you have to worry about, as much as you have to worry about the damned thing shattering.

Re:How about (0)

Anonymous Coward | more than 2 years ago | (#40303311)

450mm wafers actually have to be thicker than their 300mm brethren to keep from warping.

Re:How about (1)

Bacon Bits (926911) | more than 2 years ago | (#40304757)

Bigger wafers means less waste around the edges where the rectangular chips meet the circular wafer edge. This becomes very important for larger chips such as image sensors. (Not sure if the new process will be used for that, though.) Also, many manufacturing steps are applied to the wafer as a whole, and having wafers with over 2.25 times as many chips makes those steps cheaper on a per-chip basis.

Cheaper per-chip, yes, but if the production volume is too low or the cost per wafer overtakes the benefit of the added area, then it's not financially viable. And it has to subsume the costs of retooling all your chip production itself from 300mm to 450mm. What if wafers that size oxidize too unevenly, or etch unevenly, or fracture during cutting, or distort due to tension imparted at growth? It won't matter if the individual wafer has 2.25 times more usable area if it ends up being 2.5 times more expensive to bring a chip based on that to market.

I hope they (or someone else) succeeds because it will be of great benefit, but honestly I think 2017 is fairly optimistic.

Re:How about (1)

MarioMax (907837) | more than 2 years ago | (#40301777)

The new fabs being built in Oregon and Arizona are being built with the mentality of "300mm today, upgradable to 450mm tomorrow".

Re:How about (0)

Anonymous Coward | more than 2 years ago | (#40302867)

I'm just curious, but why couldn't someone just make some sort of mechanical device to grip the side of the crystal for support during growth? Then you would just have to go until the feed is gone? Why wouldn't this work?

Re:How about (1)

AussieNeil (1757216) | more than 2 years ago | (#40303217)

The process is all about creating large crystals of extremely high and tightly controlled purity. You do not want any additional source of contamination. If you look at tested wafers, you'll observe that the yield is lower around the wafer edge due to the effect of edge impurities and edge stresses.

Re:How about (0)

Anonymous Coward | more than 2 years ago | (#40304369)

what if you took a pure 300 mm crystal and machined nice wheels out of it, nice little bearing races and ball bearings of pure silicon. Yes there would be som friction and you can't use a lube for the aforementioned reason; but we're talking about pulling something out slowly. Friction shouldn't be a big problem.

Nevermind that though. My first guess was that the seed crystal would simply be wider than it was before, and thus able to handle the weight. If you pull slowly, then pull quickly, then start putlling slowly again do you get a "neck" that you can grab? I would think you can make that neck as thick as it needs to be.

Finally, since they're already using some kind of machinery to pull and rotate the cyrstal, I wouldn't think that the introduction of more machinery would necessarily cause contamination.

Bottom line? I'm inclined to believe that TSMC studies the big issues before going ahead with this project.

Re:How about (1)

Penguinisto (415985) | more than 2 years ago | (#40304985)

One word: heat.

They're pulling it directly out of a pool of molten silicon. Even the crucible melts into the mixture during the process (which is actually a good thing - the Wikipedia entry explains why, incidentally.)

Re:How about (1)

blind biker (1066130) | more than 2 years ago | (#40300759)

How about they focus on fixing their 28nm production problems before they set their eyes on lowering cost through bigger wafers.

A company such as TSMC can very easily do both: plan and build a 450 mm process and fab, and at the same time improve the 28 nm process.

Besides, foundries such as TSMC work on demand, and the cutting-edge 28 nm processing is not in high demand at the moment.

Re:How about (0)

Anonymous Coward | more than 2 years ago | (#40301291)

So fix their problems sequentially? Yeah, that's how to play catch-up.

Re:How about (4, Interesting)

tlhIngan (30335) | more than 2 years ago | (#40301413)

It's not like many of their most lucrative clients aren't hobbled at the moment by lack of supply for their top bin parts. Oh, yes they are.

Hence the move to 450mm wafers.

In semiconductor manufacturing, the cost of the wafer is basically the entire cost - around $1000 each. After processing, it's a bit more expensive. From this they cut it all up and package.

But two important factors are size of the final die, and the yield. The larger the die, the less per wafer you can make so they cost more. The yield has the same thing - the more bad chips per wafer, the more expensive it becomes because the good chips have to pay for the bad. And there's a relation between size and yield - the larger the chip, the greater the chance that it'll be bad as flaws in the silicon or manufacturing are amplified by the die area.

So a larger wafer means more chips per wafer, which gives you hopefully less cost per chip (the wafer doesn't cost that much more over the number you get).

Chips get cheaper for two reasons - enhanced yields (as processes get refined) and moving to smaller nodes (each chip consumes less die area and thus you can fit more per wafer).

For chips that are fixed-area, like say a full-frame dSLR sensor - it can mean cheaper cameras as yields get higher.

For larger die chips, like the largest FPGAs (which can easily cost $15,000+ each) it can bring down their cost. And memory is die-area-limited, so larger wafers mean they can be bigger as well.

Re:How about (1)

Kjella (173770) | more than 2 years ago | (#40302515)

Except this isn't like process improvements where you can make X% more chips using the same material, going from 300mm to 450mm is like cooking a double batch where you still need double the ingredients. There's obviously some advantages in that you get less edge compared to area (50% increase in edge, 125% in area) which means less waste and less edge yields - which are generally lower than in the center, 450mm equipment will cost more but less per die area however it's not revolutionary. Most seem to suggest a 20-25% decrease in cost, but the investment costs are huge so there's likely to be far fewer players. Intel, Samsung, TSMC, Toshiba/SanDisk and maybe one or two more.

Re:How about (1)

viperidaenz (2515578) | more than 2 years ago | (#40302281)

They're not the only ones building factories for 450mm wafers. Intel is already doing it for one. If they don't keep up with the other players in the market they won't have to worry about 28nm production problems if they have no customers. 450mm is 3x larger than 300mm, that's a pretty big cost saving there.

Re:How about (1)

Relayman (1068986) | more than 2 years ago | (#40304689)

450mm is 2.25x larger than 300mm, that's a pretty big cost saving there. There, FTFY.

TSMC (1)

Anonymous Coward | more than 2 years ago | (#40300551)

Taiwan. Semiconductor. Manufacturing. Company.

Taiwan's where it's at (1)

fiannaFailMan (702447) | more than 2 years ago | (#40300563)

Our CEO (based in Silicon Valley) makes regular trips to Taiwan. He tells me of massive developments out there, office parks the size of the city of Fremont are springing up left right and centre. Says there's this government organisation (can't recall its name) that takes in graduates as resident interns, carries out pure research, incubates new companies, and is a driving force behind the country's growth.

Anyone on here from Tawian that can confirm this? Sounds to me like they're kicking ass over there.

Re:Taiwan's where it's at (4, Funny)

Yvan256 (722131) | more than 2 years ago | (#40300949)

Sounds to me like they're kicking ass over there.

It's not like they have a choice. The government outlawed chewing gum.

Re:Taiwan's where it's at (1)

Savantissimo (893682) | more than 2 years ago | (#40301859)

You're thinking of Singapore.

Re:Taiwan's where it's at (0)

Anonymous Coward | more than 2 years ago | (#40303783)

I'll just put that link here:
http://en.wikipedia.org/wiki/They_Live#Legacy [wikipedia.org]

Re:Taiwan's where it's at (0)

Anonymous Coward | more than 2 years ago | (#40300953)

office parks the size of the city of Fremont

Do they have a Sierra Club that funds battalions of lawyers to preclude such development by abusing the legal system? I'll bet they don't.

No, instead they keep their tax burden low [wsj.com] and rely on industrial productivity for their growth.

Oh, they also use tariffs and taxes [gistnet.com] on imports to protect their domestic industry.

Amazing what you can do when you run your nation properly.

Re:Taiwan's where it's at (0)

Anonymous Coward | more than 2 years ago | (#40302129)

Yes, because if the US had hight tariffs on imports... we'd be living in circa 1965, before the emergence of the East Asian industrial dynamos that caused the price of electronics to plummet. In fact, none of those dynamos would have emerged at all. We'd still have crappy cars, and while the white upper-middle class would be marginally better off in terms of stable employment, we'd be living in a completely different world.

There's a reason so many great dystopian novels were written in the first and middle parts of the 20th century. It was a time when the mass media was so completely and obviously divorced from the utter misery of hundreds of millions of people. Even and, perhaps, especially, in the United States. But I guess if all you care about is the promise of success, instead of living it, then please, roll back the clock.

Re:Taiwan's where it's at (0)

Anonymous Coward | more than 2 years ago | (#40301967)

The organization is called ITRI, Industrial Technology Research Institute (ITRI). http://www.itri.org.tw/eng/ [itri.org.tw]

Its basically like a giant research university full of post-docs and post-masters for entry level, staff researchers, etc. They do things in addition to IC design, with many other engineering departments in various fields. They have a on-site gym building like a research university would have, etc etc. But nothing that special that a big research university wouldn't have. I've been there, it's nice, but not as sunshiney as your optimistic post makes it sound.

Re:Taiwan's where it's at (0)

Anonymous Coward | more than 2 years ago | (#40301997)

Our CEO (based in Silicon Valley) makes regular trips to Taiwan. He tells me of massive developments out there, office parks the size of the city of Fremont are springing up left right and centre.

China is going to love all that infrastructure when it rolls in.

Fab wise? (4, Informative)

Sycraft-fu (314770) | more than 2 years ago | (#40302233)

It is big, but then so is the US and more cutting edge research is going on here. Intel is already on the 22nm node, and I don't mean playing with, I mean shipping chips in mass quantities to retailers and OEMs (Ivy Bridge). TSMC is on the 28nm half node currently, with plans to go to the 20nm half node about the time Intel goes to the 14nm half node.

In terms of 450mm wafers, well Intel is going there too or at least that is the plan. Fab 42 is under construction in Chandler Arizona right now and will be 14nm process, 450mm wafer. It is slated to start commercial production in 2013, and Intel has been pretty damn good about hitting its dates on fabs.

No doubt Taiwan is big for semiconductor fabrication, as TSMC is one of the biggest fab-for-hire outfits out there. However if you think all the R&D is going on there, all it means is you've not paid attention to Intel. They are ahead of all other processes currently (and usually are) and they upgrade at a fantastic rate. They do real ground breaking research too, and have to as they are usually leading the pack. One cool thing they have in their latest process is multi-gate transistors, which is a first for CPUs as far as I know.

Mod parent up (1)

fiannaFailMan (702447) | more than 2 years ago | (#40302585)

Thank you

Re:Fab wise? (0)

Anonymous Coward | more than 2 years ago | (#40310775)

You forgot the mention that Intel is the only chip fab that maintained R&D investments through the 2008-2010 crash, all of the other companies had drastic cut-backs.

Gosh (1)

geekoid (135745) | more than 2 years ago | (#40300659)

going to a new technology for an industry has risks? [YOU DON'T SAY]

Development effort (0)

Anonymous Coward | more than 2 years ago | (#40300667)

It is great to see such a large development effort in one area of computer manufacture that has the ability to deliver an immediate linear cost reduction. Some quick math here. The surface area of a face of a 300mm and 450mm wafer is as follows: 300mm=70684 sqmm, 450mm=159038 sqmm. This is a 125% increase in surface area and only a marginal 1414/942 50% increase in edge length, so proportionally less lost parts for a given die shrink. A 100% increase would cut part cost in half so this improves on even that by almost 30%.

Mathematics is your friend.

JJ

Earth Quakes? (0)

Anonymous Coward | more than 2 years ago | (#40300677)

Isn't Taiwan earthquake prone ?
Why build a U$ 10 Billion factory there ? Will it be on low ground near a river as well ?

Re:Earth Quakes? (1)

Yvan256 (722131) | more than 2 years ago | (#40300931)

Are you suggesting to build this thing in Australia so that in case of flooding the water will drop into space?

Re:Earth Quakes? (1)

stox (131684) | more than 2 years ago | (#40301165)

I would be more worried about attacks from the mainland.

Fuck Everything (5, Funny)

oldhack (1037484) | more than 2 years ago | (#40300691)

We're doing 500mm!

Re:Fuck Everything (0)

Anonymous Coward | more than 2 years ago | (#40301267)

Panel saws in cabinet shops cut 4x8 foot sheets. Why not start there since the cutting is by laser and the grabbing is by robot anyway. 1220x2440mm. 1872% the output and no edge loss. Chips, the next generation.

Re:Fuck Everything (1)

thexile (1058552) | more than 2 years ago | (#40306423)

or vagina

No wonder (0)

Anonymous Coward | more than 2 years ago | (#40300907)

Wafers... chips... no wonder programmers are always hungry.

Re:No wonder (2)

Jeng (926980) | more than 2 years ago | (#40300941)

That doesn't explain the fondness for Ramen Noodles.

Larger wafers or larger lithographies/processes? (-1)

unixisc (2429386) | more than 2 years ago | (#40301061)

I can understand if TSMC, or anyone else, were moving from 8" to 12" wafers. But going to 450nm? That is 0.45 microns, and is something from the late 90s. The only thing such processes would be good for is making really simple circuitry w/ really few gates, or low density memory. Something like 2M bits of RAM. So what exactly are they gaining migrating to a higher lithography, when the trend is to go lower?

Re:Larger wafers or larger lithographies/processes (2)

cheese_boy (118027) | more than 2 years ago | (#40301205)

I can understand if TSMC, or anyone else, were moving from 8" to 12" wafers.
This is going to 18" wafers. (~17.7 inch - close enough that I'd assume it'd be called "18 inch")
300mm wafer are sometimes called 12" wafers. And is what many/most use now.
If someone were moving from 8" to 12" (200mm to 300mm) it's not news at this point - they're years behind others in moving.

Re:Larger wafers or larger lithographies/processes (1)

unixisc (2429386) | more than 2 years ago | (#40306397)

Thanks to you and everyone else in this thread for clearing it - somehow, I didn't notice it was 450mm. Incidentally, is TSMC the first company to move to 18" wafers? Or have Intel and other leading fabs moved there already?

Re:Larger wafers or larger lithographies/processes (1)

serbanp (139486) | more than 2 years ago | (#40301513)

Remember when your mammy told you to proofread before hitting the "Submit" button? Should have listened then, now you look like an idiot for mis-reading the 450mm wafer size for 450nm (presumably the minimal process feature), then trying to be a smart-ass about the perceived incompetence of one of the the largest silicon manufacturers in the whole world.

Re:Larger wafers or larger lithographies/processes (1)

unixisc (2429386) | more than 2 years ago | (#40306351)

Oh, thanks, I did misread it as 450nm rather than 450mm. I'm more used to hearing about 6", 8", 12" wafers, so I'd have thought that using 16" would have been more like it. Thanks, 'mammy'! Now the article makes a lot more sense.

Re:Larger wafers or larger lithographies/processes (0)

Anonymous Coward | more than 2 years ago | (#40301611)

Why do people who have clearly absolutely no understanding of the manufacturing process of processors such as yourself think they can comment and criticise such a decision?
A larger wafer will increase the number of dies that can be produced, the die yield ( non-defective dies) and reduce the cost of dies.
The size of the wafer is not the size of the die. You could have a 1m wafer and produce 22nm CPU dies on it.

Re:Larger wafers or larger lithographies/processes (1)

MarioMax (907837) | more than 2 years ago | (#40301969)

You could have a 1m wafer and produce 22nm CPU dies on it.

Hell, I wouldn't be surprised if we see 1m wafers within our lifetime.

Re:Larger wafers or larger lithographies/processes (1)

unixisc (2429386) | more than 2 years ago | (#40306359)

I doubt that they'll grow anywhere near that, b'cos beyond a point, the risk of breakage of the wafers as they get transported from fabs to assembly is much higher. Maybe they'll increase the #wafers that constitute a lot?

Re:Larger wafers or larger lithographies/processes (0)

Anonymous Coward | more than 2 years ago | (#40302241)

You misunderstood - they are using a 22nm (that's nanometers) process, but they are manufacturing dies 450mm (that's millimeters) in diameter, or about 17 inches, as other have said. I would make fun of you for your reading comprehension, but you're far from the only person who misread the units, and the units look very similar anyway.

Re:Larger wafers or larger lithographies/processes (0)

Anonymous Coward | more than 2 years ago | (#40302471)

Why would you make fun of him when you aren't getting anything right either?

Re:Larger wafers or larger lithographies/processes (1)

artor3 (1344997) | more than 2 years ago | (#40304545)

I would love to see a 450 mm die. More than that, I'd love to see the probe card used to test it.

Re:Larger wafers or larger lithographies/processes (1)

unixisc (2429386) | more than 2 years ago | (#40306375)

Why use millimeters to define the wafer sizes when they are growing, not shrinking? Initially, we used to use microns to define lithographies, but when we got to 0.25 microns, we started using nm. In the case of wafer sizes, since we went from 6" to 8" to 12" to now 16", why not use cm to describe their sizes - 15cm, 23cm, 30cm and 45 cm? And thanks for not making fun of my reading comprehension - the units do look similar, and in the late 90s, I was working w/ a company who was at that time in the 0.45 micron process, which would be 450nm. So it didn't look that far fetched, which is why I was surprised.

Small cookies? (1)

arielCo (995647) | more than 2 years ago | (#40301415)

Quoth TFS:

from the those-are-some-small-cookies dept

A ~18" cookie [google.com] is small to you? Did /. outsource to Brobdingnag [google.com] ?

Re:Small cookies? (1)

ravenscar (1662985) | more than 2 years ago | (#40302427)

And a strip!

I know next to nothing about wafer fabs, but... (1)

Gordo_1 (256312) | more than 2 years ago | (#40301771)

can someone explain to me why every generation, like changing from 45nm to 32nm lithography or changing wafer size from 300mm to 450mm or whatever takes building a brand new multi-billion dollar fab when you'd think they'd build the machinery and everything that goes along with it to um, 'scale' to some extent? Certainly there must be machines in these fabs that can be re-programmed to handle changing requirements.

Re:I know next to nothing about wafer fabs, but... (3, Interesting)

MarioMax (907837) | more than 2 years ago | (#40301941)

Being that I work in Intel's Fab 32, I can speak on authority on this.

Smaller lithography means you need much better process control and tighter control limits. Machines that can produce quality die for a 45nm lithography might not get the job done at 32nm, and machines that work at 32nm lithography might not work for 22nm, at least not without some serious upgrades to your existing machines, process controls, etc. It is not a trivial task to perform a die shrink, even without architecture changes.

Also changing wafer sizes (from 300mm wafers to 450mm wafers) DOES require new buildings, or complete retrofits of your existing buildings. It is not a trivial task to convert a fab from one wafer size to another; you practically need to rebuild your fab starting from scratch. Nevermind the need to completely retool your fab (virtually all existing 300mm tools will not support 450mm wafers).

Re:I know next to nothing about wafer fabs, but... (1)

oldhack (1037484) | more than 2 years ago | (#40317973)

Hey Mario, maybe you can enlighten me and the rest of us here.

How labor intensive is silicon fabs? I had thought it was capital-intensive rather than labor-intensive and yet so many fabs are off-shored. Is it the water consumption/the enviro regulations?

Re:I know next to nothing about wafer fabs, but... (1)

iotaborg (167569) | more than 2 years ago | (#40301959)

Because all of the tools improve over time. The next generation plasma etching system will provide cleaner, more consistent etches. The next generation metal deposition systems deposit more quickly and more uniformly. As we move process generations, the tolerances and requirements on all these other processes also increases, and better processing is required to support a smaller process and result in good yields.

Re:I know next to nothing about wafer fabs, but... (1)

iotaborg (167569) | more than 2 years ago | (#40302005)

Also I should add, a fab is a considerable investment, they create chips for more than one process generation. Thus when it's time to update the fab to a newer process generation, all the tools are essentially ancient. For example, Intel has older 65 nm fabs running (obviously not producing i7s but for other items such as system controllers).

Re:I know next to nothing about wafer fabs, but... (1)

viperidaenz (2515578) | more than 2 years ago | (#40302459)

Especially when you're trying to move to a 14mn process. The silicon atoms are only 0.2nm wide...When you're building cmos structures and your transistors are supposed to have 5 silicon atoms per gate and one has 6 and the other has 4 that's a huge variation that could ruin your whole chip.

Re:I know next to nothing about wafer fabs, but... (0)

Anonymous Coward | more than 2 years ago | (#40310859)

1) They need to re-tool to use a smaller process, but can some times tweak to get a half-node reduction
2) They can use the old-tools to produce other things like chipsets/flash/etc, instead of bleeding edge expensive chips.
3) The tools they use determine a lot of how the building is designed.

In the end, just build a new building.

The impressive thing about a 450-mm wafer. . . (1)

dtmos (447842) | more than 2 years ago | (#40302527)

. . .is that it's cut from a single silicon crystal (called a boule [wikipedia.org] ), two meters long, weighing several hundred kilos, with a defect density so low that it is commercially useable to make chips 25 mm on a side, 0.5 mm thick, with 20 nm feature size.

Seems like they're on schedule (1)

dtmos (447842) | more than 2 years ago | (#40302565)

"Intel Corp., Samsung Electronics and TSMC today announced they have reached agreement on the need for industry-wide collaboration to target a transition to larger, 450mm-sized wafers starting in 2012." -- 6 May 2008 [phys.org] .

Die's per Wafer estimation (1, Insightful)

shuz (706678) | more than 2 years ago | (#40302705)

My estimates put the Die's per Wafer at:
300mm = 58615762400 DPW
450mm = 10228963043666936 DPW
If the newest 22nm process is used. By the time the factory gets up and running there may be even better efficiencies that could be adapted. It is an expensive venture but at some point either the economics work out or you need to build a new factory anyways. It is good to see progress.

Re:Die's per Wafer estimation (1)

Relayman (1068986) | more than 2 years ago | (#40304727)

Please check your calculations again. You're so far off that you must not be thinking right.

Re:Die's per Wafer estimation (1)

bill_mcgonigle (4333) | more than 2 years ago | (#40304961)

My estimates put the Die's per Wafer at:
300mm = 58615762400 DPW

Show your work! :)

(300/2)^2*pi/160 [wikipedia.org] =442 [google.com] and that's assuming no room for cutting/packaging/waste.

Re:Die's per Wafer estimation (1)

Anonymous Coward | more than 2 years ago | (#40306169)

Disclaimer: working in the industry.

Die per wafer on 300mm wafer: 50 to 500, depending on the product...
I don't even want to know how you get those numbers

Re:Die's per Wafer estimation (0)

Anonymous Coward | more than 2 years ago | (#40309823)

It can be a lot more than that. I have one product right now that's getting >6000 dpw. GP is still wildly off though.

Shouldn't be beaten any time soon (0)

Anonymous Coward | more than 2 years ago | (#40303435)

450mm ought to be enough for anyone.

450mm wafers (0)

Anonymous Coward | more than 2 years ago | (#40303799)

I was going to make a joke about how appallingly stone-aged 450mm process microchips would be, given that the size of the components after etching is measured nowadays in nanometers, at a millionth the value of millimeters, knowing full-well that they're referring to the size of the wafer, the substrate upon which many, MANY microchips are generally etched, (or however they do it).

But then that mini flame war broke out over whether or not people know the difference between the letters m and n, or between the multiples being indicated by the metric prefixes milli versus nano... or whether the milli was being used correctly... and it just ruined the fun. Ugh...

Stop bringing up sub-100 nm litho... (0)

Anonymous Coward | more than 2 years ago | (#40304585)

News flash: sub100 nm processing is done on a very very very very small quantity of silicon out there. Yep, that's right, Intel does not produce all the fancy wonderful "low-tech" little chips you see in normal things outside of computers: embedded systems, advanced sex toys, that casio watch your grandma regifted to you... the goal here is to bring standard, cheap, low power (i.e. >200 nm subthreshhold CMOS) process blocks to an even cheaper state. As for yield... of course there will be epic losses when the gears start turning, but its not like you are sitting at the cutting edge for the more finicky processes like litho and etch.

love,
me, a materials scientist

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