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Mass Production of 450mm Wafers Bumped Back Again: 2018

Unknown Lamer posted about 2 years ago | from the shiny-discs-from-the-future dept.

Hardware 67

Taco Cowboy writes with news on the slipping schedules in the move toward both larger wafers and 3D integrated circuits in the semiconductor fab world. From the articles: "TSMC ... said it planned to start mass-producing next-generation 450mm wafers using advanced 10-nanometer technology in 2018. The advanced 10-nanometer chips could first be used in mobile devices and other consumer electronics, like game consoles, that demand high-performance and low power consumption. The plan was included in the latest technology roadmap unveiled by TSMC about one year after the chipmaker attributed its delay in making 450mm wafers, originally scheduled in 2015, to semiconductor equipment suppliers' postponement in developing advanced equipment for manufacturing amid the industrial slump. Chipmakers can get 2.5 times more chips from a 450mm wafer than from a 300mm wafer ... The industry's gradual migration toward 3D ICs with through-silicon vias (TSV) is unlikely to happen until 2015 or 2016, according to sources at semiconductor companies. Volume production of 3D ICs was previously estimated to take place in 2014. Leading foundries and backend assembly and test service companies have all devoted much of their R&D efforts to TSV development, and are making progress. The major players are believed to be capable of supporting 3D ICs by 2014, but the emerging technology going into commercial production may not take place until around the 2015-16 timeframe." Probably one of the most interesting presentations at HOPE9, "Indistinguishable From Magic: Manufacturing Modern Computer Chips," covered modern semiconductor fabrication and why these things are cool. If you're interested in more background (what do all of those TLAs mean?), check out the slides / audio (or attached video of the presentation from YouTube).

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It's all lies! (2, Funny)

fuzzyfuzzyfungus (1223518) | about 2 years ago | (#41234779)

As we all know, however much They don't want us to, the pace of 'innovation' in semiconductor fabrication is based almost entirely on the reverse engineering of artefacts taken from crashed Grey spacecraft.

Unfortunately, a recent downturn in the tourism sector of Theta Epsilon Minus, caused by the booming popularity of direct neural hedonostimulator technology, has sharply reduced our supply of samples...

Re:It's all lies! (2, Funny)

Quakeulf (2650167) | about 2 years ago | (#41235397)

For some reason, I can only think of this: "It's only wafer-thin!"

Re:It's all lies! (2)

Gilmoure (18428) | about 2 years ago | (#41235647)

It's pronounced: wauffer

Shameless Spam (2, Funny)

puddingebola (2036796) | about 2 years ago | (#41234787)

Don't care about the latest technology, they will never improve on the technology in Nilla Wafers http://www.nabiscoworld.com/Brands/brandlist.aspx?SiteId=1&CatalogType=1&BrandKey=nilla&BrandLink=/nilla/&BrandId=76&PageNo=1 [nabiscoworld.com]

Silicon Chips, Yum . . . (1, Funny)

wooferhound (546132) | about 2 years ago | (#41234943)

I like Peanut Butter on my Nilla Wafers
But
Prefer Nacho Cheese dip for my Silicon Chips

450mm (0)

Hatta (162192) | about 2 years ago | (#41234821)

That's almost half a meter. That's gong to be one big CPU.

Re:450mm (0)

MickyTheIdiot (1032226) | about 2 years ago | (#41234869)

the electricity resistance will be VERY LOW.

Re:450mm (1)

slick7 (1703596) | about 2 years ago | (#41240673)

the electricity resistance will be VERY LOW.

Resistance is futile. - The Borg

Re:450mm (2)

bws111 (1216812) | about 2 years ago | (#41234973)

Uh, it's wafer, not chip, size.

Re:450mm (0)

E. Edward Grey (815075) | about 2 years ago | (#41235003)

And this, kids, is why it's important to get your units right. 1) It f*cks up your math, and 2) it opens you up to mockery.

Re:450mm (2)

bws111 (1216812) | about 2 years ago | (#41235029)

The units ARE right. The WAFERs will be 450mm. Today they are 300mm.

Re:450mm (1)

SomeJoel (1061138) | about 2 years ago | (#41239289)

The units ARE right. The WAFERs will be 450mm. Today they are 300mm.

Or 200mm, or 150mm... It really quite depends on the manufacturing equipment in the fab and the target market for the devices (not everything manufactured on a wafer is a "chip"). Rumors of 200mm's demise have been quite premature.

Re:450mm (1)

unixisc (2429386) | about 2 years ago | (#41245743)

They were usually referred to as 6", 8", 12" wafers. Now they will be 18". I really don't see the point in measuring them in mm, when the wafer sizes only tend to grow, while die sizes shrink, resulting in even more die/wafer. Measuring them in cm or dm would make more sense. Not to forget that nanometers are nm, which is easy to confuse w/ millimeters mm

Re:450mm (4, Funny)

Desler (1608317) | about 2 years ago | (#41235135)

It's even more important when you attempt to mock people for wrong units when the units are actually correct.

Re:450mm (1)

wooferhound (546132) | about 2 years ago | (#41237077)

When they launched a probe to Mars a few years ago, It crashed because it was designed using Wafer units, but the software was using Chip Units.

Intel's first 450mm wafer fab is set to open 2013 (5, Interesting)

Anonymous Coward | about 2 years ago | (#41234987)

Called D1X (development, but also production like previous "X" fabs) in Oregon, with a second to follow. 450mm wafer production will likely hit volume levels by 2014, just not at the foundries listed in the story.

Price conscious, volume manufacturers like semi foundries would be more willing to push back adoption dates if the investment isn't likely to pay for itself. Most of their business is usually on n-1 or n-2 process nodes. This changeover just happens to be particularly expensive and may not yet make economic sense for another 2-3 years.

Re:Intel's first 450mm wafer fab is set to open 20 (0)

Anonymous Coward | about 2 years ago | (#41235069)

That's because Intel is years ahead of the other foundries and has been for some time. The spend countless billions a year on their fab processes.

Re:Intel's first 450mm wafer fab is set to open 20 (0)

Anonymous Coward | about 2 years ago | (#41235983)

So do other manufacturers.

Re:Intel's first 450mm wafer fab is set to open 20 (1)

baka_toroi (1194359) | about 2 years ago | (#41236061)

I don't think TSMC spends as much as Intel on R&D.

Re:Intel's first 450mm wafer fab is set to open 20 (2)

Desler (1608317) | about 2 years ago | (#41236723)

Intel's R&D budget alone is around 70% of TSMC's total yearly revenue for example. Also, if you look up rankings of R&D spending by technology companies Intel's is basically the second highest just behind Microsoft.

Re:Intel's first 450mm wafer fab is set to open 20 (1)

CycleMan (638982) | about 2 years ago | (#41237161)

That's because Intel is years ahead of the other foundries and has been for some time. The spend countless billions a year on their fab processes.

Per Intel's January 2012 earnings report, their plan for this year is:
Capital spending: $12.5 billion, plus or minus $400 million
R&D spending: approximately $10.1 billion.

Which, compared to the size of my bank account, is "countless" :)

Re:Intel's first 450mm wafer fab is set to open 20 (1)

filthpickle (1199927) | about 2 years ago | (#41239645)

R&D spending: Hrair dollars.

you countless comment reminded me I guess

Re:Intel's first 450mm wafer fab is set to open 20 (5, Interesting)

YoopDaDum (1998474) | about 2 years ago | (#41235637)

You should take this Intel announcement with a big handful of salt. Intel doesn't make the waver producing machinery, they get it from companies like ASML.

Now, there's been a big struggle between companies like Intel that wanted 450mm earlier, and the tool makers who sank a lot of money on the move to 300mm before and don't want to be burned again in the move to 450mm. The Intel announcement above was to put pressure on the tools providers. It didn't worked out in the end.

All this got sorted out between big boys recently, with Intel, TSMC and Samsung investing a lot of money in ASML to speed-up the availability of 450mm. But the accelerated roadmap has nothing to do with the announcement you quote, just look at it from ASML direct [asml.com] (slide 14). The 450mm process development tools are worked on starting mid-2015 and production equipment is available beginning of 2018. Exactly what is said in the TFA.

450mm is important as it is the only known step that will bring the cost of chips down. Other planned changes (finer processes, 3D chips...) increase performance but also cost. But 450mm requires huge upfront investments, so you need large volumes to recoup it and it will require a big upfront spending. Which is why a lot of people are pushing back. Intel has both high volumes, high margins and deep pockets so they're the most eager to get started. But as you can see, even with their backing it's not that simple and fast.

Re:Intel's first 450mm wafer fab is set to open 20 (3, Insightful)

CaptBubba (696284) | about 2 years ago | (#41237021)

The lithography is one aspect but what about the deposition/etching equipment? It is spread across multiple vendors and getting them all to support 450mm is going to be one heck of a challenge when for the most part they have only just gotten 300mm production perfected. The chip manufacturers won't/can't settle for 450mm tools that don't hit or exceed the quality of work produced by current 300mm tools because the process nodes now depend on that quality to produce working chips. Maintaining anisotropic plasma etch selectivity or deposition thickness uniformity on over double the area without resorting to much slower processing is going to be a really tough target to hit.

Re:Intel's first 450mm wafer fab is set to open 20 (1)

Algae_94 (2017070) | about 2 years ago | (#41237637)

I'm without mod points today, but you bring up an extremely important issue. Uniformity of processes across the surface of a 450mm wafer will be very difficult to achieve. I thought it was a pain in the ass to adjust some epitaxial processes for 200mm wafers when I was still working in the semi industry. I can't imagine the hassle of going to 300mm let alone 450mm. Litho is much easier as it's really just an optical process. Ensuring uniform reactor temperature, or solution chemistry across half a meter is a lot harder.

Re:Intel's first 450mm wafer fab is set to open 20 (1)

CaptBubba (696284) | about 2 years ago | (#41238303)

Exactly, once the wafer is chucked and aligned litho is really only concerned with little 40mm by 80mm blocks of the wafer and the rest is just step and repeat. Several years ago when I left the industry the 300mm litho tools were already fully capable of introducing exposure-by-exposure correction offsets, with different correction maps depending on what exposure system the wafer ran on for a previous exposure layer. However everything is always focused on the exposure side because they are the most expensive equipment in terms of wafers produced per hour per $ of cost due to all those fancy Zeiss optics.

I remember some plasma etch and CVD engineers singing the praises of 300mm, but I think that was mostly because the wafer flats were replaced by notches and better automation keep their equipment consistently loaded. The Chemical Mechanical Planarization engineers however were never having a good time and that is going to be a beast and a half for 450mm.

Re:Intel's first 450mm wafer fab is set to open 20 (0)

Anonymous Coward | about 2 years ago | (#41236477)

No. D1X is just 450mm ready. There are no 450mm production tools available and the top equipment suppliers are only now working on prototype 450mm tools. It takes a minimum of 2 years for Intel to ramp a process and they need a full fab of production 450mm tools to do so. But before then they need a pilot line to play around with. Since they do not have any of this now in late 2012 there is no way they will have anything ramping in 450mm by 2014.

I know this because I work in the equipment industry and 450mm is still top secret and not mentioned at all in press releases. 450 pilot lines are setup at IMEC and the Albany CNSE but many of the tools are from smaller vendors that don't really have a chance in hell of making it into Intel's production line.

Re:Intel's first 450mm wafer fab is set to open 20 (1)

stevesliva (648202) | about 2 years ago | (#41237871)

No. D1X is just 450mm ready.

Similarly, I think the GlobalFoundries fab in Malta, NY is supposedly "450mm ready" or maybe the annex will be. But regardless, "450mm ready" doesn't mean all that much.

That would be interesting (1)

Taco Cowboy (5327) | about 2 years ago | (#41245367)

It would be very interesting to have Intel running a 450mm wafer FAB when there is no one supplying the FAB machines !!

Of course 450mm is delayed (0)

mr1911 (1942298) | about 2 years ago | (#41235047)

There are few products that need that kind of production. For everyone else it is just too damn expensive.

Re:Of course 450mm is delayed (3, Informative)

MozeeToby (1163751) | about 2 years ago | (#41235197)

Um, no. Larger wafers are a cost savings measure. 450mm means that you end up with fewer incomplete chips on the edges of your wafer, which in turn increases your yield. No one is stamping out a single CPU on a 450mm wafer.

Re:Of course 450mm is delayed (0)

Anonymous Coward | about 2 years ago | (#41236285)

I think the parent was referring to the initial cost of investment. 450mm is attractive for companies like Intel or TSMC who pump out huge volume, but for "smaller" manufacturers (flash memory fabs for example) the price is too steep right now.

Increasing wafer size to 450mm creates all sorts of problems that drive up the cost of manufacturing equipment. Intel recently had to throw lots of money at the the industry leader for lithography *ASML to speed up development. Chip manufactures (usually) do not make their own production machines and must rely on fab equipment companies to develop actual manufacturing technology.

*ASML has practically a monopoly of something called immersion lithography. You need their machine to make any of the recent technology nodes.

Re:Of course 450mm is delayed (1)

Algae_94 (2017070) | about 2 years ago | (#41237675)

It's not just lithography equipment. Every single piece of equipment needs to be upgraded. Chemecal etch baths need to be bigger. Measurement equipment needs to be capable of taking 450mm wafers. Process reactors need to be bigger. The shipping containers that hold the wafers need to be bigger. Don't forget, at this size (and weight) a cassette of wafers will never be moved around the fab by hand, the robots that transport the wafers all need to be upgraded to handle the new size.

This is basically like requiring an entirely new fab.

Re:Of course 450mm is delayed (5, Insightful)

hankwang (413283) | about 2 years ago | (#41236725)

450mm means that you end up with fewer incomplete chips on the edges of your wafer,

A standard die is 26x33 mm, which is much larger than the vast majority of the chips; most dies already contain multiple chips. Therefore, the edge loss is not as big a deal as you would think.

What is more of a cost saver is that most of the processing steps (applying photo resist, developing the resist, etching, ion implantation, annealing, and so on) are relatively easy to scale up to larger wafers, thereby reducing the process costs per unit of wafer area.

A big exception here is the lithography process, which gets significantly harder for bigger wafers, since it involves rapidly moving a wafer around with nanometer accuracy. A bigger wafer requires a bigger, stiffer, and therefore heavier wafer stage. ASML manufactures lithography tools that can do up to 175 wafers per hour [asml.com] (300 mm diameter) per hour, with an accuracy ("overlay") of 5.5 nm; that is about 3 dies per second. To give an idea of the scale: imagine that a vehicle is moving at 100 km/h, making multiple sharp turns per second, and tracks the ideal trajectory within 500 nm. And then the customer says: nice that you can do that with a sports car, but it's too small; can you build a heavy SUV that can do the same thing? (So there, a car analogy)

This is why Intel, TSMC, and Samsung have invested into ASML to speed up the development of 450 mm litho tools.

Disclosure: I work for ASML, but the above opinions are my own.

Re:Of course 450mm is delayed (0)

Anonymous Coward | about 2 years ago | (#41238319)

> 3 dies per second
You mean 3 dies per minute.

Re:Of course 450mm is delayed (1)

CaptBubba (696284) | about 2 years ago | (#41239637)

No, three per second and that is a conservative estimate. 175 wafers per hour means 21 seconds per wafer and with 75 exposures on a wafer you are looking at around nearly four per second average, although some of those might be off the edge and not yield. The actual exposure speed is faster because there is some dead time when the wafer is not actively under the optics and exposing. Then remember that an exposure can have multiple chips in it (because no processor out there is 26mm by 33mm) and you will start to get a real grasp of how fast the production goes.

The equipment is insanely fast and a modern fab will complete millions of operations per day. It just takes thousands of steps to make a modern processor so the only real way to make it profitable is to make each step as fast as possible and have enough of material at each stage in the production line so no equipment goes idle except for maintenance, yet there isn't so much that you have a glut anywhere.

Re:Of course 450mm is delayed (2)

CaptBubba (696284) | about 2 years ago | (#41238643)

The ability of the Twinscan to maintain the positional accuracy that it can at the speeds and accelerations involved is just jaw dropping. I'm sure they are telling you that you cannot do the logical thing to keep the forces manageable by dropping the scan speed much (if any) in the changeover from 300mm to 450mm because everyone would freak out as the whole point is to maximize exposures per second while minimizing wafer exchange time. I do think that other processes will also have some pretty awful trouble getting to 450mm though. Think of all that wafer warping, layer uniformity trouble, and backside contamination!

(former litho overlay engineer, your hard work helped make my vector maps happy)

Re:Of course 450mm is delayed (1)

hankwang (413283) | about 2 years ago | (#41240225)

keep the forces manageable by dropping the scan speed much (if any) in the changeover from 300mm to 450mm because everyone would freak out as the whole point is to maximize exposures per second while minimizing wafer exchange time.

Indeed; I guess we would feel sorry if the whole tool needs to be slowed down (reticle stage, source power, metrology) just because the wafer stage cannot keep up. The ambitions should be even higher: by the time that 450 mm tools go to the market, the overlay targets will likely be tighter than they are today - they follow Moore's law.

I do think that other processes will also have some pretty awful trouble getting to 450mm though.

It could very well be that I am underestimating the technological hurdles in the other processes because I hear about ASML's technological challenges every day. :-)

Re:Of course 450mm is delayed (1)

unixisc (2429386) | about 2 years ago | (#41246319)

Except that larger wafers are priced almost exponentially higher, so that whatever savings one gets in terms of more die/wafer is more often offset by the differences in wafer pricing. This is at least during the initial life cycle of the wafers. They probably try to recoup the initial costs of investment in all that equipment, and wafer pricing drops often accompanies equipment depreciation more than market demands.

Re:Of course 450mm is delayed (1)

mr1911 (1942298) | about 2 years ago | (#41248369)

You misunderstood. The amount of die per wafer is a drastic increase. If you are selling chips that get into the next popular consumer device you need that kind of output. There majority of things run do not have that kind of volume, so 450mm turns out to be a barrier to entry rather than a cost benefit.

Re:Of course 450mm is delayed (1)

gman003 (1693318) | about 2 years ago | (#41235377)

450mm wafers don't mean 450mm products. It means you can fit 50% more chips onto a single wafer - you just upped your production rate by 50%. More than that, actually - because that's the diameter, not the area. The area just went up by 225%, assuming I did my math right.

A large chip right now is 150mm^2. So now instead of fitting 450 of them onto one wafer, you can fit 1000 of them. Bam. Productivity just doubled. Small CPUs are in the 70mm^2 range, and other chips are even smaller.

Re:Of course 450mm is delayed (1)

Desler (1608317) | about 2 years ago | (#41235443)

It's 250% as the summary states. 50 x 50 is not 225.

Re:Of course 450mm is delayed (0)

Anonymous Coward | about 2 years ago | (#41235697)

WRONG.

300mm ^ 2 = 90,000 mm ^ 2
450mm ^ 2 = 202,500 mm ^ 2

202,500 mm ^ 2 / 90,000 mm ^ 2 = 2.25

It's not an increase of 250%. It's not an increase of 225%. It's an increase of 125% or 2.25 times more chips. So if you could make 100, now you can make 225.

Re:Of course 450mm is delayed (1)

Algae_94 (2017070) | about 2 years ago | (#41237739)

I don't mean to pile on here, but even if your logic was correct and the increase was 50 x 50. 50 x 50 = 2500.

The diameter is increasing by 1.5 times (50% larger) the area is proportional to the radius squared so the increase is (1.5x1.5)= 2.25 times more area, 225% of the smaller size, or 125% more than the smaller size.

Re:Of course 450mm is delayed (1)

cheesybagel (670288) | about 2 years ago | (#41239193)

  • AMD Bulldozer Zambezi (32 nm): 319mm^2
  • Intel Sandy Bridge-EP-8 (32 nm) : 435mm^2
  • IBM POWER7 (45 nm) : 567mm^2
  • Intel Tukwilla (65 nm) : 698.75mm^2.

Eventually this will be how Moore's law ends. (1)

HornWumpus (783565) | about 2 years ago | (#41235453)

In a steaming pile of lies.

Eventually they will run into a technical problem that they can't solve. Marketers will continue to say 'it's all good, we're just pushing it back another year'.

I'm not saying this is the end. But it will eventually hit a wall.

Re:Eventually this will be how Moore's law ends. (3, Funny)

Gilmoure (18428) | about 2 years ago | (#41235683)

Exactly! Why do some people even try and make things better? I mean, are they mental or something? We should gather up all these folks that won't give up and refuse to recognize the futility that is man and shoot them off on a rocket ship to another planet!

Re:Eventually this will be how Moore's law ends. (0)

Anonymous Coward | about 2 years ago | (#41236827)

Yes, there are more elements waiting to be found in the periodic table of elements, and we'll find smaller atoms too. This isn't about some nebulous "making things better", it's about real physics and the real world. Has anyone found anything better than jet engines to push planes around the atmosphere? We can make better ones, but forever? We can't find new materials or new fuels for them.

There are limits, however much this hurts the feelings of techno-fetishists such as yourself.

Re:Eventually this will be how Moore's law ends. (2)

Gilmoure (18428) | about 2 years ago | (#41236943)

Exactly! Periodic Table of Elements is complete! The party will be "soon". All forms of propulsion through the air has been figured out. DOD and DOE are cancelling all further ramjet experiments. All you science and engineering students in college? Shoulda' taken Post-Raphelite Literature, loosers!

Re:Eventually this will be how Moore's law ends. (1)

HornWumpus (783565) | about 2 years ago | (#41237057)

Everything has limits. When you approach the practical limits you don't already know the limit is there.

Everything is on time, until it is late.

Don't expect Intel to tell you 'we're hitting a technical wall' expect them to tell you 'it's going to take another year, but will be even better when we get there'. They have investors to manage.

Re:Eventually this will be how Moore's law ends. (0)

Anonymous Coward | about 2 years ago | (#41237971)

So you are saying that there can be new elements in the Periodic Table? Like, for instance, between carbon and nitrogen, there's a hidden element that we haven't found yet? That's like saying there's a whole number hiding between 4 and 5.

I note that not many ramjet systems exist these days... due to material limits. I further note you can't even spell "losers". You also seem to think that every single science and engineering student in college will necessarily find something new.

Has anyone found a new fundamental force lately? Something as useful as the photon let's say? Hmm?

All we're getting good at is squeezing every last bit of engineering out of our physics. Like ramjets who are explained by 19th century physics.

But I guess to you, when we reach (we already have) atomic-level electronics, we'll just use quarks, right?

Turbojets came around after WWII and flew entire generations on planes, then the turbofan came along. How many people have flown on ramjets? Hm? Same time frame though. Explain that.

Re:Eventually this will be how Moore's law ends. (2)

Gilmoure (18428) | about 2 years ago | (#41238157)

Just because da Vinci came up with the idea of the helicopter hundreds of years ago does not mean we shouldn't have worked atmaking it happen. Sure, some things are more difficult than others but that doesn't mean we should give up. Where would y'all like to live? A world where we only go after low hanging fruit or one where, despite many failures, we keep trying and improve on what we have done before?

Bottom line: On May 31, 2012, the International Union of Pure and Applied Chemistry (IUPAC) approved the addition of flerovium and livermorium to the periodic table of elements. The two new elements were discovered during collaborative research carried out by scientists from the Lawrence Livermore National Laboratory in the United States and the Joint Institute for Nuclear Research in Russia. An official announcement describing the new names of the two elements will be published in the July 2012 issue of the IUPAC journal, Pure and Applied Chemistry.

ScienceDaily (Aug. 16, 2012) — A team of scientists led by Carnegie's Lin Wang has observed a new form of very hard carbon clusters, which are unusual in their mix of crystalline and disordered structure. The material is capable of indenting diamond. This finding has potential applications for a range of mechanical, electronic, and electrochemical uses.

Wright Patterson AFB has confirmed in an official press release that Tuesday’s test of the Waverider X-51A unmanned hypersonic missile has failed. Launched from a B-52 bomber over Point Mugu Naval Air Warfare Center Sea Range at 11:36 AM PST, the separation from the bomber and ignition of the X-51A’s rocket booster went as planned. However, 16 seconds into the flight a fault occurred in one of the missile’s control fins before the scramjet could start, resulting in the craft losing control, and the X-51A was today officially reported as "lost."

Re:Eventually this will be how Moore's law ends. (1)

unixisc (2429386) | about 2 years ago | (#41246441)

Essentially, what drives it is
  1. Price pressure from customers who use these chips to manufacture end products, be it laptops, tablets, phones, GPS modules, routers, set top boxes, cable modems, et al
  2. Improved performance or lower power requirements from engineers who need the shrinkage to achieve one of these 2 goals

I do agree that there will come a point where no more shrinkage is possible - when we start getting into counting atoms, we're pretty much there. By then, hopefully, the market is also satisfied that products would have attained their optimal price points, and don't have much more demand in terms of either low power consumption nor performance. Yeah, there will be a section for whom more is always better, but once they get to the point of diminishing returns, there'll be less demand to shrink things. I think this 45cm wafers will be the last.

Re:Eventually this will be how Moore's law ends. (0)

Anonymous Coward | about 2 years ago | (#41236179)

Huh? Lies?? You're a moron.

Secondly, this has nothing to do with Moore's law.

Thirdly, nobody except morons like you think that Moore's law is actually some fundamental constant.

TEN nanometer? (0)

Anonymous Coward | about 2 years ago | (#41235489)

Oh god, how did they fix the problems? Isn't that the sizes where tunneling, leakage and even casimir become really major?

Hey, software engineers (-1)

Anonymous Coward | about 2 years ago | (#41235513)

Don't you ever feel ashamed that you basically rest on the hardware progress to allow your bloated software to run? Do you still think you are engineers after looking at that video? You're children, playing in the sandbox adults create for you.

Re:Hey, software engineers (-1)

Anonymous Coward | about 2 years ago | (#41236041)

Yeah yeah, mod me down you wankers. Without hardware and the real physicists, engineers and technicians developing it you'd have to get real jobs with real results.

Re:Hey, software engineers (0)

Anonymous Coward | about 2 years ago | (#41236807)

Without the software guys, quite a few of you hardware guys would be out of a job too. Demand for hardware would be pretty low if we went back to entering commands through switch panels again.

Re:Hey, software engineers (0)

Anonymous Coward | about 2 years ago | (#41238417)

He's just trolling. If he knew anything about hardware engineering he would know that current hardware would be impossible to design without the aid of software tools.

Good; there's no need. (2)

markhahn (122033) | about 2 years ago | (#41235659)

current wafers still yield large numbers of current-sized chips. and for the most part, chip architects are not primarily limited by available area: relentless process shrinks bring, if anything, more transistors than they know how to use. sure, you can always throw on more cache, especially L3. but the main issues today are power and IPC/TLP-type efficiency, not space. the K20 team at NVidia might disagree, but they _should_ be pushing the bounds, since their target is less cost-sensitive HPC, not commodity/gaming.

in short, the action is in litho, process, transistor topology, power and microarchitecture, not the number of chips spoiled by the edges.

Re:Good; there's no need. (5, Informative)

tlhIngan (30335) | about 2 years ago | (#41236151)

current wafers still yield large numbers of current-sized chips. and for the most part, chip architects are not primarily limited by available area: relentless process shrinks bring, if anything, more transistors than they know how to use. sure, you can always throw on more cache, especially L3. but the main issues today are power and IPC/TLP-type efficiency, not space. the K20 team at NVidia might disagree, but they _should_ be pushing the bounds, since their target is less cost-sensitive HPC, not commodity/gaming.

in short, the action is in litho, process, transistor topology, power and microarchitecture, not the number of chips spoiled by the edges.

That's correct for transistor-limited (aka pin-limited) chips, but not so for area-limited chips.

Yes, just like we have CPU-bound software and IO-bound software, we have area-limited and pin-limited chips. Pin-limited chips are where the I/O balls are keeping chips from becoming bigger - you see this as CPUs, SoCs, chipsets and other utility chips (many bus architectures are redesigned to be more conservative on their pin usage - why consume 64 pins when you can use 16).

Area limited chips are where the actual silicon area limits their usage - too big and flaws mean lower yields, too small and your devices may not meet requirements. These kind of devices are typically memory devices - the storage array is the largest consumer of area (the logic fits neatly around it) and the larger you can make the storage array, the bigger the memory.

Memory devices are also some of the most dense, transistor wise (a CPU has tons of "random logic" that means wiring is what keeps transistors spread apart, not transistor density). For a given process node, if you can double the area of the storage array, you double the storage.

And memory devices cover a wide gamut - from imaging devices (CCDs, CMOS), standard DRAMs and SRAMs, and EEPROM-style memory (including flash memory).

Basically the amount of storage you can stick is limited by area (double area, double storage, eseentially), but if you make the area too big, yields go down as the impact of an imperfection destorys the entire chip.

A larger wafer has more area available, and since wafer costs are mostly fixed (a single wafer costs anywhere from $1000-3000 or so), the number of good chips has to pay for it all. The more good chips (higher yield), the cheaper the cost.

A larger wafer means more chips can be made, so cheaper overall memory devices - which translate to cheaper SSDs, cheaper DRAMs, digital cameras with larger sensors, dSLRs with full-frame sensors at a budget price (this one especially - the sensor is the most expensive part because it's genuinely a HUGE piece of silicon and only a handful make it out of a wafer, even allowing for bad pixels).

For other chips, a larger area does allow for more wiring, which is what dominates chip design, not transistors. If you take something like an FPGA - the thing limiting it IS area - wiring area is extremely limited.

Re:Good; there's no need. (1)

stevesliva (648202) | about 2 years ago | (#41238013)

Yes, just like we have CPU-bound software and IO-bound software, we have area-limited and pin-limited chips. Pin-limited chips are where the I/O balls are keeping chips from becoming bigger - you see this as CPUs, SoCs, chipsets and other utility chips (many bus architectures are redesigned to be more conservative on their pin usage - why consume 64 pins when you can use 16).

You sounds like a good advocate for TSVs. That said, defects in memory devices probably don't limit the maximum chip size all that much-- memory devices can contain lots of redundant elements to repair defects. Simple chips/wafer cost considerations--because no one wants to pay much for memory--probably has a lot more to do with it. It's just straight-up cost limiting area, not defect density. And when it comes to the push for 450mm, it's not necessarily higher yield that's expected, but lower cost per chip and higher fab throughput. Yield may actually decrease at first, but processing cost per chip would ideally outweigh that.

Re:Good; there's no need. (0)

Anonymous Coward | about 2 years ago | (#41236991)

Those that I know working on machines used for various processing of the wafers and lithography are constantly complaining about how little time they have to process each wafer. A bunch of options and new tech doesn't get used in their production machines, because it would slow down the process too much. They get told things like one step needs to be done in 30 seconds or they need to do a wafer a minute to keep things economical. Doubling the production rate by larger area where other processes are the same could make a decent cost difference. Alternatively, doubling the amount of chips on a wafer, allowing for production processes to take twice as long to get the same production speed would allow for new technologies to be introduced.

Re:Good; there's no need. (1)

Algae_94 (2017070) | about 2 years ago | (#41237831)

going to a larger wafer size isn't about spoiled edge chips. If that were really an issue, we would be using square wafers. The ingots could be sliced up into squares quite easily.

The real advantage is that you produce more chips per wafer, and ideally, the per wafer processing time is unchanged, This has nothing to do with how good the chips are, or what they do. It is just to make more of them and make them cheaper.

I suppose if anyone really wanted to and could find the right equipment, they could make high end chips on 75mm wafers. Well maybe not those little 3" ones, but at least 100mm wafers could still have good equipment available. The reason they don't is that people using 300mm wafers would make close to 10 times as many wafers in the same amount of time.

No need. (1)

MaWeiTao (908546) | about 2 years ago | (#41236243)

If the move to bigger wafers is driven strictly by increased efficiency there's no incentive to rush to adopt it. It's no different than rushing out to buy a marginally more fuel efficient car. It's going to take years to make up the difference in savings, if that ever even happens.

The move to 450mm wafers is a massive investment. Twelve years ago I had the opportunity to visit a new 300mm foundry for TSMC's big Taiwanese competitor UMC. The entire line was built around that size; everything from the cases that hold the wafers, to the tracks that transport them to the units that do the lithography. So you can't just swap out a production line. They'd almost certainly just build a new facility, which is not trivial in it's own right. But again, not much reason to bother if all it will enable you to do is get more units on one wafer.

And that isn't even accounting for the technical difficulties in simply making larger wafers. A lot of problems have already been addressed at the current sizes, but the bigger sizes introduces a host of new challenges. And when it comes down to it, there's 10-nanometer chips don't inherently require a bigger wafer.

Given the fact that foundries have ramped down production because of decreased demand there's even less incentive to go bigger.

Re:No need. (0)

Anonymous Coward | about 2 years ago | (#41238327)

"But again, not much reason to bother if all it will enable you to do is get more units on one wafer."

You are likely unfamiliar with the semiconductor industry. The name of the game is how many die you can produce and at what performance. Having 2.5X the number of dies on each wafer isn't a "marginal" improvement like the car example you give.

you F4il It (-1, Redundant)

Anonymous Coward | about 2 years ago | (#41237265)

sai3 0ne FreeBSD FreeBSD's
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