Beta
×

Welcome to the Slashdot Beta site -- learn more here. Use the link in the footer or click here to return to the Classic version of Slashdot.

Thank you!

Before you choose to head back to the Classic look of the site, we'd appreciate it if you share your thoughts on the Beta; your feedback is what drives our ongoing development.

Beta is different and we value you taking the time to try it out. Please take a look at the changes we've made in Beta and  learn more about it. Thanks for reading, and for making the site better!

iPhone 5 A6 SoC Teardown: ARM Cores Appear To Be Laid Out By Hand

Unknown Lamer posted about 2 years ago | from the museum-of-modern-art-accepting-vlsi-layouts dept.

Iphone 178

MrSeb writes "Reverse engineering company Chipworks has completed its initial microscopic analysis of Apple's new A6 SoC (found in the iPhone 5), and there are some rather interesting findings. First, there's a tri-core GPU — and then there's a custom, hand-made dual-core ARM CPU. Hand-made chips are very rare nowadays, with Chipworks reporting that it hasn't seen a non-Intel hand-made chip for 'years.' The advantage of hand-drawn chips is that they can be more efficient and capable of higher clock speeds — but they take a lot longer (and cost a lot more) to design. Perhaps this is finally the answer to what PA Semi's engineers have been doing at Apple since the company was acquired back in 2008..." Pretty picture of the chip after using an Ion Beam to remove the casing. The question I have is how it's less expensive (in the long run) to lay a chip out by hand once instead of improving your VLSI layout software forever. NP classification notwithstanding.

cancel ×

178 comments

Sorry! There are no comments related to the filter you selected.

A6 hand layout awesome performance sweet (-1, Troll)

busyqth (2566075) | about 2 years ago | (#41457045)

Good job Samsung!

Re:A6 hand layout awesome performance sweet (0, Insightful)

Anonymous Coward | about 2 years ago | (#41457477)

Good job Samsung!

For what, exactly reproducing what Apple gave them?

Re:A6 hand layout awesome performance sweet (3, Funny)

Anonymous Coward | about 2 years ago | (#41457537)

Android users usually get laid by hand.

Re:A6 hand layout awesome performance sweet (0)

Anonymous Coward | about 2 years ago | (#41459141)

But at least they can do it with anyone they want.

Carpal tunnel (5, Funny)

Anonymous Coward | about 2 years ago | (#41457051)

That must be a very fine tipped resist pen...

Re:Carpal tunnel (5, Funny)

Anonymous Coward | about 2 years ago | (#41457173)

Yeah I bet their ARMs are tired after making that.

Re:Carpal tunnel (1)

93 Escort Wagon (326346) | about 2 years ago | (#41457279)

Wish I had mod points...

Although I'm not sure which way I'd mod you - I laughed and groaned at the same time.

Re:Carpal tunnel (1)

MarkRose (820682) | about 2 years ago | (#41458411)

These stories always have an armful of puns.

Re:Carpal tunnel (5, Funny)

grcumb (781340) | about 2 years ago | (#41458723)

Wish I had mod points...

Although I'm not sure which way I'd mod you - I laughed and groaned at the same time.

Mod down. Clearly GP is doing more ARM than good.

Automation versus human instinct (4, Insightful)

Taco Cowboy (5327) | about 2 years ago | (#41458343)

The question I have is how it's less expensive (in the long run) to lay a chip out by hand once instead of improving your VLSI layout software forever.

No matter how much improvement on VLSI layout software their output can't match that of hand-laid layout by those who know what they are doing.

The VLSI layout software are like compilers. The final compiled code relies on two factors - the source-code input and the built-in "rules" of the compilers.

A similar case is in software programming - The source code from a so-so programmer compiled by a very very good compiler will result in a "good-enough" result.

It's good enough because it gets the job done.

However, a similar program by an expert Assembly Language programmer would have left "good enough" behind because the assembly language programmer would know how to tweak his code using the most efficient commands, and cut out the 'fats" by optimizing the loops and flows.

Re:Automation versus human instinct (4, Insightful)

CastrTroy (595695) | about 2 years ago | (#41458789)

I think you underestimate how good compilers have become. Also, the "expert assembly language programmer" probably would work at 1/100 the pace of a programmer in something more high level like C++. It would probably be next to impossible to write an entire modern operating system, web browser, or word processor in assembly language. Sure for some very small sections of code you can optimize at the assembly level, but you can't write a whole program in assembly. Also, if a person can recognize some optimization, then that optimization can be added to the compiler, which means that a compiler can probably always at least come within a very close margin of where the human could get, and it could probably do better, because a compiler can remember a lot more optimizations than any human can.

Re:Automation versus human instinct (2)

Taco Cowboy (5327) | about 2 years ago | (#41459005)

I think you underestimate how good compilers have become

Nope.

I know how good compilers have become - especially compilers from the makers of the particular processor the program supposed to be run on.

But I guess you may have missed the "so-so programmer" I've mentioned.

Even the top-line compiler can't produce a top-notch program if been fed source code by a so-so programmer.

There are a lot of ways to write programs.

From the so-so programmers, the source code read like a bowl of bland noodles.

But from a top-notch programmer, he or she would know how to structure his/her program in such a manner similar to what a top-notch chef can get out of a bowl of bland noodles.

Re:Automation versus human instinct (2)

hazydave (96747) | about 2 years ago | (#41459131)

Well, the real answer is that it's not an either/or scenario. Chip design teams design and layout chips based on off-the-shelf tools, layout expertise, etc. Silicon compilers are also constantly improved, but a completely different set of people are involved. Not sure about today's Apple, but the 80s/90s Apple probably would have done it both ways. In fact, even now I think about it, and the way the Intrinsity guys seem to work, it makes sense.

This is sometimes done in PCB layout. Sure, some types of layout, like RF, are pretty much always done by hand. Today's successful autorouters work from a large set of design constraints that describe the circuit at a high level. You may get a layout sufficient fir a prototype in a week rather than the month the hand layout would take. On a tight schedule, that's two free weeks of bring up.

So it might well be that they ran the silicon compiler, tweaked and simulated the piss out of the design, in parallel with the much longer hand layout. Maybe a bit like hand optimizing compiled code with downcoding/recoding and profilers.

As for hand layout/coding always beating compilers, not in practice. One is certainly a time constraint... the compiler will produce a better end product below a certain time limit. Just where that line is drawn depends on the coder and the complexity of the process. As the CPU/PCB/chip rule sets grow, the compiler does better than the human, assuming it can efficiently factor in the rule set. Naturally, when it can't, you need the personal touch. Until it's expanded to embrace the new rules...like vector or GPGPU coding today. The other factor is of course architecture .. human time is usually better spent on the big picture items, architecture and algorithm. No sense hand coding for a 10% improvement in quality when the same time spent on design might yield 100%.

Not to mention the JIT factor -- code is compiled on the fly for the specific CPU and system in use. Custom DSP pipelines created based on the problem at hand. A complex math problem is targeted,on the fly, to somewhere between 32 and 4096 parallel processing elements. Compilers always win here.

Costs (5, Informative)

girlintraining (1395911) | about 2 years ago | (#41457217)

The question I have is how it's less expensive (in the long run) to lay a chip out by hand once instead of improving your VLSI layout software forever. NP classification notwithstanding.

Coding in assembly still remains a superior method of squeezing extra performance out of software. It's just that few people do it because compilers are "good enough" at guessing which optimizations to apply, and where, and usually development costs are the primary concern for software development. But when you're shipping hundreds of millions of units of hardware, and you're trying to pack as much processing power in a small and efficient form factor, you don't go with VLSI for the same reason you don't go with a compiler for realtime code: You need that extra few percent.

Why assembly ... (4, Insightful)

perpenso (1613749) | about 2 years ago | (#41457353)

The question I have is how it's less expensive (in the long run) to lay a chip out by hand once instead of improving your VLSI layout software forever. NP classification notwithstanding.

Coding in assembly still remains a superior method of squeezing extra performance out of software. It's just that few people do it because compilers are "good enough" at guessing which optimizations to apply, and where, and usually development costs are the primary concern for software development. But when you're shipping hundreds of millions of units of hardware, and you're trying to pack as much processing power in a small and efficient form factor, you don't go with VLSI for the same reason you don't go with a compiler for realtime code: You need that extra few percent.

I like to view things as a little more complicated than just applying optimizations. IMHO assembly gets some of its biggest wins when the human programmer has information that can't quite be expressed in the programming language. Specifically I recall such things in the bad old days when games and graphics code would use fixed point math. The programmer knew the goal was to multiply two 32-bit values, get a 64-bit result and right shift that result back down to 32 bits. The Intel assembly programmer knew this could be done in a single instruction. However there wasn't any real way to convey the bit twiddling details of this fixed point multiply to a C compiler so that it could do a comparable operation. C code could do the calculation but it needed to multiply two 64-bit operands to get the 64-bit result.

Re:Why assembly ... (1)

Anonymous Coward | about 2 years ago | (#41457549)

You should be using C++; that way you can define a class for fixed-point numbers, and just overload the * operator with a function that uses inline assembly code.

Re:Why assembly ... (0)

Anonymous Coward | about 2 years ago | (#41457625)

You just hurt my head...

Re:Why assembly ... (1)

busyqth (2566075) | about 2 years ago | (#41457809)

You just hurt my head...

*sigh*

Re:Why assembly ... (1)

Anonymous Coward | about 2 years ago | (#41457683)

You should be using C++; that way you can define a class for fixed-point numbers, and just overload the * operator with a function that uses inline assembly code.

That is just an implementation detail of how you write the assembly code. The need to use assembly in such a circumstance remains the same whether one use a separate .asm file, inline asm in C or classes with inline asm in C++.

Re:Why assembly ... (1)

marcosdumay (620877) | about 2 years ago | (#41458289)

Just remember to veryfi your assignment operators and copy constructors, otherwise they'll lose more time than your asm will gain.

Re:Why assembly ... (1)

MightyYar (622222) | about 2 years ago | (#41458513)

... and then you'd write the assembly - same as you'd do if it was called by C or Python.

Re:Why assembly ... (1)

loufoque (1400831) | about 2 years ago | (#41457639)

You don't need to use assembly for this, you can just use built-ins or intrinsics.

Assembly is only useful if you want to control register usage.

Re:Why assembly ... (1)

perpenso (1613749) | about 2 years ago | (#41457853)

You don't need to use assembly for this, you can just use built-ins or intrinsics. Assembly is only useful if you want to control register usage.

Which are really just alternative ways to write a line or two of assembly code. They are just conveniences, you are still leaving the C/C++ language and dropping into architecture specific assembly.

Re:Why assembly ... (1)

loufoque (1400831) | about 2 years ago | (#41457891)

Which are really just alternative ways to write a line or two of assembly code.

it is vastly different since you leave register allocation to the compiler, which means you can still use inlining and constant propagation.

Re:Why assembly ... (1)

perpenso (1613749) | about 2 years ago | (#41457935)

Which are really just alternative ways to write a line or two of assembly code.

it is vastly different since you leave register allocation to the compiler, which means you can still use inlining and constant propagation.

An alternative with an advantage but still fundamentally programming at the architecture specific assembly level rather than the C/C++ level.

Re:Why assembly ... (0)

Anonymous Coward | about 2 years ago | (#41457991)

Code generated by intrinsics is usually pretty subpar and comes with limitations, though.

Re:Why assembly ... (0)

Anonymous Coward | about 2 years ago | (#41457841)

I like to view things as a little more complicated than just applying optimizations. IMHO assembly gets some of its biggest wins when the human programmer has information that can't quite be expressed in the programming language.

Then there's things like non-standard calling conventions. Or, whether your C/C++ compiler is passing one or more arguments to a function through registers instead of the stack, etc.

Doing abs() with assembly and no conditional statements, versus C/C++ [go4expert.com]
MOV EAX,[LOCAL.1] ; put a signed value in the EAX register
CDQ
SUB EAX,EDX ; done, EAX contains the result

Re:Fixed point multiply (2)

gr8_phk (621180) | about 2 years ago | (#41458575)

The proper syntax for that is (using x64 types) something like:

int a,b,z;

z = (int)(((long long)a * b) >> 32);

I'm assuming int is 32bit and long long is 64. Even though a is promoted to a larger type and also b, good compilers know that the upper half of those promoted variables are not relevant. They will then use the 32bit multiply, shift the 64bit result and store the part you need. I still do fixed point for control systems and find using 16bit signals and 32bit products is faster in C than floating point even on some embedded PPC chips - never mind the fixed point DSPs we use where the shifts cost nothing. Anyway, this syntax also worked on a HC12 compiler back in '98 or so. It's still hit or miss, but generally works on parts where this stuff is still common.

Re:Costs (2)

pclminion (145572) | about 2 years ago | (#41458217)

Coding in assembly still remains a superior method of squeezing extra performance out of software.

I'd say it's more important to be able to read assembly than to write it. I do a lot of performance optimization of C++ code, and mostly it involves looking at what the compiler generates and figuring out how to change the source code to produce better output from the compiler. Judicious use of const, restrict and inline keywords can make a huge difference, as can loop restructuring (although the compiler can do a fair amount of loop restructuring itself, sometimes it needs help).

It's been a long time since I saw compiler output that made me go "WTF, is this compiler dumb or something?" In fact, it tends to figure things out that are pretty amazing (to me, at least). I once saw a compiler eliminate an entire lookup table which it determined wasn't necessary, an impressive feat of compile-time execution modeling.

Re:Costs (1)

Anonymous Coward | about 2 years ago | (#41459075)

Coding in assembly doesn't always beat the compiler. I learned this in '90 or '91. I'd been doing both C and assembly for 10 years. We were on a Nat Semi 16032 (or 32016, they changed names). Had a tight loop that had to process a scanned line of text into FAX in a hard limit of a few ms, and succeeded about 80% of the time. I spent a month trying to both write my own assembly, and tweak the compiler's output. I never came close to what the compiler was spitting out.

I don't remember how we fixed it, but coding that loop in assembler wasn't the answer.

contrary to popular opinion... (0)

Anonymous Coward | about 2 years ago | (#41457229)

...companies thinking in the long run prefer an intelligent or well-trained workforce to automation and minimum wage.

And before you retort, no - Foxconn workers are far above "minimum wage" for China.

Automation is the win for *some* tasks (2)

perpenso (1613749) | about 2 years ago | (#41457573)

...companies thinking in the long run prefer an intelligent or well-trained workforce to automation and minimum wage.

In general your point does have some merit but it really does depend on the specific task at hand. My grandfather was a master welder. However for *some* of the tasks that he used to perform a robotic welding system would be a better idea.

Ahh.. idiotic Slashdot Editor "commentary" (-1, Flamebait)

CajunArson (465943) | about 2 years ago | (#41457235)

The question I have is how it's less expensive (in the long run) to lay a chip out by hand once instead of improving your VLSI layout software forever. NP classification notwithstanding.

It's easy moron... unless you plan on being a one-hit wonder, you'll most likely want to eventually come up *another chip* that will require the hand-layout process to be made all over again! Wow!

Re:Ahh.. idiotic Slashdot Editor "commentary" (0)

Anonymous Coward | about 2 years ago | (#41457811)

What kind of moron are you?
If you improve the CAD software now, you get the better chip now, and any chip you design in the future.
It's called a non-recurring cost.
If you do it separately for each chip it becomes a recurring cost.
Maybe they plan on this being the last chip they ever make?

Re:Ahh.. idiotic Slashdot Editor "commentary" (1)

Lunix Nutcase (1092239) | about 2 years ago | (#41458003)

Or maybe with their $100 billion in cash and 10s of billions of dollars in revenue that they can easily absorb the costs?

Site is down (0)

Anonymous Coward | about 2 years ago | (#41457263)

Site is already down due to the Slashdot effect.

Re:Site is down (0, Redundant)

busyqth (2566075) | about 2 years ago | (#41457295)

Site is already down due to the Slashdot effect.

Don't kid yourself. The Washington Post linked to it too.

Re:Site is down (1)

ThatsMyNick (2004126) | about 2 years ago | (#41457347)

It is still called the Slashdot effect though.

Re:Site is down (1)

Anonymous Coward | about 2 years ago | (#41458223)

Not really. This site used to have enough traffic to take down a web server, but not anymore.

Re:Site is down (3, Funny)

lister king of smeg (2481612) | about 2 years ago | (#41457747)

and their tech section is run by taco so it could be counted as a sort of pseudo-slashdot effect they have as well

Re:Site is down (1)

busyqth (2566075) | about 2 years ago | (#41457819)

and their tech section is run by taco so it could be counted as a sort of pseudo-slashdot effect they have as well

Thank you. *sigh*

Re:Site is down (5, Informative)

sexconker (1179573) | about 2 years ago | (#41457393)

I've put the picture (which is what everyone wants) up here:
http://i.imgur.com/vqCAu.jpg [imgur.com]

Re:Site is down (2)

thammoud (193905) | about 2 years ago | (#41457557)

Yup. That definitely is hand made.

Re:Site is down (3, Funny)

busyqth (2566075) | about 2 years ago | (#41457745)

Actually not only is that one hand made, each and every A6 is lovingly hand made. That's why they're top quality.

Re:Site is down (2, Funny)

Lumpy (12016) | about 2 years ago | (#41458071)

But they are not lovingly hand made on the thighs of Virgins... That is reserved for El Presidente' Processors.

Hand-made? (1)

Anonymous Coward | about 2 years ago | (#41457271)

They must have tiny hands.

Re:Hand-made? (1)

MobileTatsu-NJG (946591) | about 2 years ago | (#41457339)

Those poor Foxconn workers. I bet Apple hires kids to work at Foxconn! I hear they also burn the bodies of the ones that die to heat the factory.

Re:Hand-made? (0)

Anonymous Coward | about 2 years ago | (#41457419)

And they process the charred remains into a nutritious food slurry.

Re:Hand-made? (1)

Anubis IV (1279820) | about 2 years ago | (#41457629)

Nonsense. They're made into nutritional supplements that you can pick up in a rectangular bar form, just as with the other nutritional supplements supplied by the government. The ones you're talking about are called Green.

Re:Hand-made? (3, Funny)

Type44Q (1233630) | about 2 years ago | (#41458179)

They're made into nutritional supplements that you can pick up in a rectangular bar form

With rounded corners?

Chip design not black-or-white (5, Informative)

whoever57 (658626) | about 2 years ago | (#41457343)

Today, chips are nearly always laid out using advanced, CAD-like software â" the designer says he wants X cache, Y FPUs, and Z cores, and the software automagically creates a chip. Hand-drawn processors, on the other hand, are painstakingly laid out by chip designers.

There are a lot of layout methodologies that are between the (frankly mythical) "X cache, Y FPUs, and Z cores" and fully hand layout. The top level may have more or less amounts of hand assembly, some blocks can be hand optimized, etc.. Usually, there is lots of glue logic which must be designed in RTL, synthesized and only then laid-out. And, for most blocks the process to create the logic design (RTL or perhaps gates) is separate from the process of laying-out these blocks. So there is room for manual involvement in each of the steps.

And made by Samsung (-1)

Anonymous Coward | about 2 years ago | (#41457379)

Laughed when read that the A6 is made in Samsung fabs.

Display, processor, flash... hmmm... not much that isn't Samsung in that shiny new "apple" iphone.

Re:And made by Samsung (1)

jbolden (176878) | about 2 years ago | (#41457445)

Display is LG. Flash is mostly Hynix and Toshiiba.

Re:And made by Samsung (-1, Troll)

busyqth (2566075) | about 2 years ago | (#41457795)

Display is LG. Flash is mostly Hynix and Toshiiba.

Yeah, but the software is Samsung, and everyone knows that's what really counts.

Re:And made by Samsung (1)

Plumpaquatsch (2701653) | about 2 years ago | (#41458043)

Display is LG. Flash is mostly Hynix and Toshiiba.

Yeah, but the software is Samsung, and everyone knows that's what really counts.

The CPU is manufactured by Samsung, and that's what really counts for Fandroids.

Re:And made by Samsung (5, Funny)

busyqth (2566075) | about 2 years ago | (#41458099)

Display is LG. Flash is mostly Hynix and Toshiiba.

Yeah, but the software is Samsung, and everyone knows that's what really counts.

The CPU is manufactured by Samsung, and that's what really counts for Fandroids.

Nah, I was referring to the well sourced fact that iOS is actually just a gimped version of Android.
Remember Schmidt was on the Apple board, and he provided preview copies of Android to Jobs.

Re:And made by Samsung (1)

Lunix Nutcase (1092239) | about 2 years ago | (#41458383)

Word to the mods: this person was joking.

Re:And made by Samsung (4, Informative)

Lunix Nutcase (1092239) | about 2 years ago | (#41458023)

Display is LG, Flash is Hynix, the RAM is from Elpida and their chip is their own design with Samsung just acting as a fab no different than Global Foundries or TSMC.

Looking closely (5, Informative)

taniwha (70410) | about 2 years ago | (#41457389)

Looking closely I see a bunch of ram - probably half laid out by hand (caches) - and a many may small standard cell blocks almost certainly not laid out by hand - what I don't see is an obviously hand laid out datapath (the first part of your CPU you spend layout engineers on) - look for that diagonal where the barrel shifter(s) would be. There are some very regular structures (8 vertically) that I suspect are register blocks.

Still what I see is probably someone managing timing by synthesizing small std cell blocks (not by hand), laying those blocks out by hand then letting their router hook them up on a second pass - - it's probably a great way to spend a little extra time guiding your tools into doing a better job to squeeze that extra 20% out of your timing budget and give you a greater gate density (and lower resulting wire delays)

So - a little bit of stuff being done by hand but almost all the gates being lait out by machine

'by hand' - not really. (5, Informative)

queazocotal (915608) | about 2 years ago | (#41457401)

This is not by hand.
To take a programming analogy, it's looking at what the compiler generated, and then giving it hints so the resultant code/chip is laid out as you expect.

Chips stopped being able to be laid out 'properly' by hand some time ago.

Doing this has much the same benefits as doing it with code.
You know stuff the compiler does not.
You can spot silly stuff it's doing, that is not wrong, but suboptimal, and hold its hand.

Re:'by hand' - not really. (5, Funny)

Sulphur (1548251) | about 2 years ago | (#41457761)

This is not by hand.
To take a programming analogy, it's looking at what the compiler generated, and then giving it hints so the resultant code/chip is laid out as you expect.

Chips stopped being able to be laid out 'properly' by hand some time ago.

Doing this has much the same benefits as doing it with code.
You know stuff the compiler does not.
You can spot silly stuff it's doing, that is not wrong, but suboptimal, and hold its hand.

Or grab its ARM.

Designed not made by hand (1)

aNonnyMouseCowered (2693969) | about 2 years ago | (#41457979)

Not being a chip expert, the following made me think twice over whether some dextrous East Asian factory workers used tweezers to lay out the circuits of each and every chip rolling down the assembly line:

"Hand-made chips are very rare nowadays, with Chipworks reporting that it hasn't seen a non-Intel hand-made chip for 'years.'"

The phrase "hand-made chips" is misleading because it gives the impression that, similar to the way motherboards are still assembled by hand, the production of CPUs involve human fingers coming into direct contact with the silicon.

Instead of teams of wondrous elves etching the microscopic pathways of electrons, we are treated to the less remarkable, but still impressive revelation that most chip designs are automatically spit out by high level chip design software.

Re:'by hand' - not really. (1)

drhank1980 (1225872) | about 2 years ago | (#41458067)

I always considered the day people stopped using Rubylith [wikipedia.org] to be when we stopped doing layouts "by hand".

What makes hand-made chips "faster"? (1)

Anonymous Coward | about 2 years ago | (#41457457)

IANAEE (I am not an electrical engineer).

I'm a mathematician. As I understand it, chip layout is usually done by solving a large-scale optimization problem to obtain a layout where things are packed as tightly as possible.

What I don't understand is the assertion in the summary that hand-drawn optimizations can be faster than a computed one. To me, hand-crafted optimizations can be passed to the optimizer, which will then output the tightest design based on the constraints given (with the hand-crafted optimizations incorporated). So it seems to me that hand-crafted optimizations can be as fast as computer-optimized circuit layouts... but not faster.

What am I missing here?

Note: I guess the compiler analogy would be writing something in assembly (with hand-crafted optimizations) vs. writing something in C and passing it through an optimizing compiler. But I don't know if circuit layout works like that. Or does it?

Re:What makes hand-made chips "faster"? (5, Informative)

Hatta (162192) | about 2 years ago | (#41457845)

I'm guessing that the search space is too large to brute force the optimization. For similar reasons we can't write a program that can beat a Go master. It's just too hard a problem without heuristics, and the heuristics in the human brain are better. Figure out why, and you've solved AI.

Re:What makes hand-made chips "faster"? (0)

Anonymous Coward | about 2 years ago | (#41458683)

Please mod this man up (ASIC/FPGA designer).

Re:What makes hand-made chips "faster"? (5, Informative)

marcansoft (727665) | about 2 years ago | (#41457859)

What you're missing is that chip layout is NP-complete. For anything beyond very trivial chips, no computer algorithm can yield the optimal solution in a reasonable time.

As I understand it, automated layout algorithms are still, when you get down to it, largely quite dumb. I'm sure this is oversimplifying and someone who writes place-and-route software will probably want to kill me, but the algorithm is closer to "throw stuff together, measure performance, tweak things randomly, measure performance, keep the change if it got better" than to anything likely to yield an optimal solution. Eventually, you'll converge on a decent layout, sure, but not an optimal one.

It's pretty much guaranteed that this chip wasn't completely hand-crafted (modern chips are much too complicated to do that). Instead, most likely, engineers guided the placement of major blocks and data paths, and let the automated place-and-route software choose the rest. By constraining the design based on intelligent decisions, you can guide the automated process to converge on a better solution.

Re:What makes hand-made chips "faster"? (3, Informative)

AK Marc (707885) | about 2 years ago | (#41458081)

And an incremental chip would benefit from hand-holding more than a new one. Say they tested the chip at + 50% clock speed and identified locations of instability. Then, they "by hand" took an optimized automated layout and tweaked it to improve those few specific areas. That would be a "by hand" design that didn't take too much work and gave a better result. Perhaps do the same thing, but with 50% less voltage, rather then increased speed. Then hand-optimize on that. Then compare the two and come up with something that's faster and lower power than the automated process would ever come up with.

Most algorithms I've messed with are very good at iteration, but bad at evolution (they win chess by calculating odds and values, not by analyzing the opponent and his moves).

Re:What makes hand-made chips "faster"? (0)

Anonymous Coward | about 2 years ago | (#41458531)

well as I commented elsewhere I think that's what's being done for the CPU (lots of little machine synthesised/laid blocks hand placed then machine rerouted, probably with a few tweaks) - on the other hand the GPUs there are all just seas of gates

One of the things that's happened in the past decade is that RC wire delays have come to dominate gate delays which means that the old technique of synthesis followed by place&route has had to give way to a more integrated approach - leaving many many more degrees of freedom available to the software and making it harder to make choices - there's a lot of ad-hoc smarts in there to get to a good place in a real-world reasonable time - chopping things up into pieces gives the software a small problem space to deal with.

Re:What makes hand-made chips "faster"? (2)

gr8_phk (621180) | about 2 years ago | (#41458687)

A compiler analogy. Until recently, register allocation was a hard problem better handled by human experts. Now there are polynomial time algorithms for handling it and compilers can do it optimally. I imagine the subtleties of layout make it a much harder problem to automate - similar to the difference between chess and go.

Re:What makes hand-made chips "faster"? (2)

Anonymous Coward | about 2 years ago | (#41458773)

>> automated layout algorithms are still, when you get down to it, largely quite dumb

Auto-custom layout tools are rare, good ones are usually shaped like humans.

Change 'layout' to 'placement' and I fully agree. Leave it as 'layout' and change 'dumb' to 'nearly non-existent' and I agree again. Good layout people are worth gold, they are two steps from the GDSII stream and they build working circuits from a spice deck or w/e gibberish the circuit designer dumps on them. I'm not a layout person, they just are the difference between making it work and yet another great idea.

>> It's pretty much guaranteed that this chip wasn't completely hand-crafted

Yes, agree, but this concept of by-hand is relative, by-hand back in the day was walking around in a giant room drawing transistors on sheets of the moral equivalent of mylar. Yes I was there...

Fast forward to where we have computers and cool-ish stuff: cpu houses usually break logic into 3 mushy categories, random logic synthesis (RLS), structured datapath (SDP) and full custom.

Recognizing RLS from a picture is pretty easy, blob of standard cells apparently randomly placed.

The differences between SDP and full custom (in the obviously not RAM areas) are tougher to distinguish in these pictures, not enough detail in the images and difficult to tell what is actual layout and what are effects of the post-mortem process.

SDP is a manually intensive process, but not nearly time consuming as full custom since you are still primarily dealing with a standard cell library and not 'rolling your own'. The visual effect is similar to full custom, regular patterns easy for the eye to distinguish.

But I am surprised by the amount of apparent white space in the pictures, which is an indirect indicator of custom blocks stitched together after their individual design is complete, typically not the case in SDP (nor obviously RLS).

So that really begs a much larger question. If it is a custom design why the hell go through all the trouble and then lose a chunk of the benefit by placing these lovingly crafted blocks in such a way? This is money, more importantly power consumption efficiency left on the table. I'm not judging but more wondering about the tradeoff choices made, could be tech, could be schedule, too far away to judge.

Working backwards from product announce, having some idea about how long this takes, full custom or SDP/custom mixture, this could be the work of that crufty crew at Intrinsity (quondam notus ut EVSX, Exponential Technology) who (apparently) did the previous work on Apple A5 in the Samsung process. The calendar time works out.

Re:What makes hand-made chips "faster"? (3, Informative)

Space cowboy (13680) | about 2 years ago | (#41458787)

As a mathematician, you ought to understand global optimization encountering local minima in a high-dimensional space. Standard tools for large-scale functional minimization are all subject to it in one form or another, and humans get to ignore all the "stuff that doesn't make sense" - machines don't have that latitude, at least with current algorithms.

Don't get me wrong, the layout and design tools are on the bleeding edge; they're as sophisticated as they come, and there's a *huge* amount of maths in how they work, but they're still crap, compared to a moderately skilled human. What they do excel at is doing all the tedious repetitive work that is typically required, and there's a *lot* of that.

Simon

Re:What makes hand-made chips "faster"? (1)

Anonymous Coward | about 2 years ago | (#41458915)

IANAEE a lot of design skills are still referred to as art. An example would be the original 64 bit athlon's where all laid out by hand to get the last mhz in.
Expert systems are great, but subtle performance, be it building a race motor, hand crafting in assembly an important loop or designing a processor, humans still win.

It's a level of indirection (2)

Kjella (173770) | about 2 years ago | (#41457483)

The question I have is how it's less expensive (in the long run) to lay a chip out by hand once instead of improving your VLSI layout software forever.

You can teach a small kid to ride a bicycle. The same kid has no chance to program a robot into doing the same motion and balancing. It's the same order of magnitude in difference with VLSI layout, a person can lay out the circuits but it's almost impossible to describe to the computer all the reasons why he'd lay it out that way. It's not easy controlling anything well through a level of indirection, that's true for most things.

As for being "less expensive", companies don't just have expenses but they have income too. If you can increase revenue because you got a better chip that sells more, they're willing to pay a higher cost. Companies care about profits, not expenses in isolation. Those tiny improvements to the compiler, how valuable are they to Apple in 10 years? 20 years? As opposed to an optimized chip which they know how much is worth right now.

lets look at a different analogy (3, Insightful)

v1 (525388) | about 2 years ago | (#41457695)

I don't think bicycle riding is a very good analogy to this problem. How about cooking, which is a procedural step-by-step operation? Little hints the recipe can give you like "preheat oven to 350 degrees" can be a tremendous time-saver later. If you didn't know to do that, you'd get your dish ready and then look at the oven (off) and click it on and sit back and wait 20 minutes before placing it in the oven. A dish that was supposed to be 60 minutes start to serve is now going to take 80 minutes due to a lack of process optimization.

Compilers have the same problem of not knowing what the expectations are down the road, and aren't good at timing things. Good expereinced cooks can manage a 4 course meal and time it so all the dishes are done at the right time and don't dirty as many dishes. Inexperienced cooks are much like compilers, they can get the job done but their timing and efficiency usually have much room for improvement.

Re:lets look at a different analogy (2)

mspohr (589790) | about 2 years ago | (#41457889)

I think we need a car analogy.
Following iLost maps while drunk driving is like using a compiler.
On the other hand, following the directions from your mother in law in the back seat is like a fish.
YMMV

Re:lets look at a different analogy (1)

magarity (164372) | about 2 years ago | (#41458027)

Time to buy a new oven if it takes 20 minutes to heat to 350.

Re:lets look at a different analogy (-1, Flamebait)

rtb61 (674572) | about 2 years ago | (#41458235)

The most appropriate thing here is the marketing analogy. Endless pointless articles about the new iPhone that's better than all the other iPhones because 'er' it makes Apple even more money. I stumbled across another article practically drooling over the new Apple proprietary connector because the plug can get stuck in either way because so many people stick their phone in backwards in a dock with the screen facing away from them (the last bit of snark is mine). Go away with the marketing Apple trying to generate the 'Cool' is dead for you, you blew it in court with those idiotic patents and trying to shut down competitors through the courts (face it in every movie et al since the beginning of time that is the tactic of the black hat bad guy). This marketing route was sort of OK through all the other iterations of iPhone but now it is just plain annoying.

News For This Nerd (5, Interesting)

History's Coming To (1059484) | about 2 years ago | (#41457547)

Brilliant, this is what I love about Slashdot, I can be the biggest geek in whatever field I pick and I will still get outgeeked! I enjoyed reading the comments above mostly because I have absolutely no idea what the detail is, and I'd never even realised that hand-drawn vs machine was a issue.

Can anyone supply a concise explanation of the differences and how it's all done? I'm guessing we're talking about people drawing circuits on acetate or similar and then it's scaled down photo-style to produce a mask for the actual chip?

Yes, I know I can just Google it, and I will, but as the question came up here I thought I'd add something to a real conversation, it beats a pointless click of some vague "like" button any day :)

Re:News For This Nerd (2)

oji-sama (1151023) | about 2 years ago | (#41457927)

Sorry, not an expert, but you might find this article (about AMD Steamroller) interesting. At least check the short "Looking Forward: High Density Libraries". They are rebuilding hand-drawn diagrams to be more efficient. http://www.anandtech.com/show/6201/amd-details-its-3rd-gen-steamroller-architecture/2 [anandtech.com]

Re:News For This Nerd (0)

Anonymous Coward | about 2 years ago | (#41457957)

I'm guessing we're talking about people drawing circuits on acetate or similar and then it's scaled down photo-style to produce a mask for the actual chip?

Not, that's not what hand drawn means, but doing it that way sounds awesome.
This is basically the difference between running the design through a placer, or choosing the placement of elements yourself.

Re:News For This Nerd (0)

Anonymous Coward | about 2 years ago | (#41458011)

Acetat films were >30 years ago, now it is all done by computers. Yes, you may now go to google and check the details...

BTW, being an RF chip designer myself (not digital, only sometimes AMS); all my circuit layouts are still done "by hand" (my hand, actually!).

Re:News For This Nerd (5, Informative)

lexman098 (1983842) | about 2 years ago | (#41458453)

The headline is attention-grabbing bullshit.

I'd believe that Intel may have in the past done manual placing and routing of custom made cells in certain key parts of their CPUs, but I can almost assure you that Apple did not place all of the standard cells in their ARM core's and then route them together manually, which is what the headline implies.

What I'm talking about here is literally placing down a hundred thousand rectangles in a CAD tool and then connecting them correctly with more rectangles which is way beyond what Apple would have considered worth the investment for a single iPhone iteration. What's more probable (and pretty standard for digital chip design) is that they placed all of the large blocks in the chip by hand (or at least by coordinates hand-placed in a script), and they probably "guided" their place and route tool as to which general areas to place the various components of the ARM cores. They might have even gone in after the tool and fixed things up here and there.

Modern chips are almost literally impossible to "lay out by hand".

Re:News For This Nerd (1)

stevesliva (648202) | about 2 years ago | (#41458477)

Can anyone supply a concise explanation of the differences and how it's all done? I'm guessing we're talking about people drawing circuits on acetate or similar and then it's scaled down photo-style to produce a mask for the actual chip?

CPU code is in RTL,verilog,VHDL, whatever-- it's in HDL. Usually these days a synthesis tool or compiler will create chip layout that implements that HDL description in standard cell logic. The standard cells are latches, NAND gates, buffers, SRAM, etc. A software tool will place and route standard cells to implement the HDL in silicon, and then iterate on timing to make sure it's fast enough. Humans don't directly do the placement of standard cells, or route wires between them. In terms of photolithography, the standard cells are the silicon transistors, and the first two levels of metal.

It looks like they're making a mountain out of the fact that the standard cells were placed by hand here, and some of the more regular and important wiring was perhaps done by hand, too. You can often take your human knowledge of where the likely performance chokepoints are and place those carefully, and you can also take your human knowledge of where the wiring congestion will be, and be careful there. You're also perhaps able to wire things a bit more creatively in that you can use wrong-way metal and perhaps less gridding. And then you can still probably tell the algorithms to take care of the rest.

In either case the standard cells themselves are often handcrafted in CAD tools, but sometimes different layout software will make them, too. It's just that with large logic chips, past that point humans are often only in the physical design loop to take care of problems the tools can't solve independently-- like massaging things that come out of synthesis too slow to meet the targeted performance, or mandating certain metal levels will be dedicated to a clock mesh. Sometimes that human intervention is just permitting the tool to suck up more power by using faster standard cells. Other times it would be revisiting the architecture in HDL, but then again throwing it over to a computer to place and route. The humans are not actually moving cells around the chip in a CAD tool.

I don't do the synthesis part of the process myself, so someone can clarify or correct me. The thing I wonder about is why the chipworks guys assume hand placement necessarily takes much longer? Looking at the layout, I'd assume the biggest tradeoff is the size of the core, not time spent on placement. It's routing a gazillion non-regular wires that is hard for humans, not placement. We can still place standard cells in a core without needing years of time, provided it doesn't need to be perfectly area-efficient.

Re:News For This Nerd (3, Informative)

slew (2918) | about 2 years ago | (#41458685)

Nobody "draws" chips by "hand" anymore. It's all being done by a computer (there are so many design rules these days humans can't do this anymore in a realistic time frame). Reticles (the photomasks) are all fractured by computer these days because rectangles aren't really rectangles anymore at these small feature sizes (we are now past the diffraction limit so masks must be "phase-shift" masks not binary masks back in the old-days).

I don't have any specific knowledge about the A6, but what is euphamistically called hand-drawn these days is often still very automated relative to the bad-old-days when people were drawing rectangles on layers to make transitors. That was the real-hand-drawn days, but even way back then you didn't actually draw them by hand, you used a computer program to enter the coordinates for the rectangles.

Quick background: now days when typical chips go to physical design, they usually go through a system called place-and-route where pre-optimized "cells" (which have 2-4 inputs and 1-3 outputs and implement stuff like and-or-invert, or register flop) are placed down by the computer (typically using advanced heuristic algorithms) and the various inputs and outputs are connected together with many layers of wires which logically match the schematic or netlist (which is the intention of the logical design). Of course this is when physics starts to impose on the "logical" design, so often things need special fixups to make things work. Unfortunatly, the fixups and the worst case wirelengths between cells conspire to limit the performance and power of the design, but just like compiled software, it's usually good enough for most purposes. Highly leveraged regularly structured components of normal designs might have libraries, specialized compilers or even have hand intervention (e.g, rams, fifos, or register files), but not the bulk of the logic.

As far as I can tell from looking at the pictures the most likely possibility is that just that instead of letting the computer place the design completely out of small cells, some larger blocks (say like ALUs for the ARM SIMD path) were created by a designer and layout engineer who probably used a lower-level tool to put down the same small cells relative to other small cells where they think is a good place to put them and tweak the relative positioning to try to minimize the maximum wire lengths between critical parts of the block. The most common flow for doing this is mostly automated, but tweakable with human intervention (this what passed for "by-hand" these days). In addition to being designed to optimize critical paths, these larger blocks are generally desgined so that they "fit" well with other parts of the design (e.g., port order, wire pitch match, etc) to minimize wire congestion (so they can be connected with mostly straight wires, instead of those that bend). Basically looking at the patterns of whitespace in the presumed CPU, you can see the structure of these larger blocks instead of big rectangles (called partitions) which have rows of cells you get when you let a computer do place-and-route with small cells.

Just like optimizing a program, there are many levels of pain you can go through and what I described above is probably the limit these days. Say if you wanted less pain, another more automated way to get most of the same benefits is to just develop a flow that hints where to put parts of the design inside the normal rectangular placement region, and let a placement engine use those hints. The designer can just tweak the hints to get better results. Of course with this method, the routing may still have "kinks" in this case because routing is not wire-pitch-matched, but you can often get 80-90% the way there. The advantage of this lesser technique is that you don't need to spend a bunch of time developing big blocks and if there is a small mistake (of course nobody ever makes mistakes), it's much, much easier to fix the mistake w/o perturbing the whole design.

FWIW, it is highly unlikely that the entire A6 CPU is done with a layout out of individual transistors instead of groups of pre-canned logical cells in larger blocks (as described above). The design rules for modern fabrication processes are such that it is extremely hard to characterize random adjacent transistors and wires (basically you need to do 3D EM-field solvers in the presence of many adjacent noise sources), so this is generally only done on highly regular structures (like rams and flip-flops) and long buses or clock trees, not irregular structures like floating-point ALUs or say a complicated branch prediction unit. Even if you could do that, the fab likely will not have any experience on tweaking process parameters to get good yield on such a tight layout so you probably won't get good yield even if you spent the time to do it.

Re:News For This Nerd (1)

Macman408 (1308925) | about 2 years ago | (#41458975)

They used to literally make a mask by hand, but then the features on the chip got smaller (on the scale of nanometers), and the chips got bigger (up to hundreds of square millimeters, holding billions of transistors). To draw the whole thing, you'd need a piece of acetate 360 meters on each side, at least. These days (and for the last couple decades), it's all CAD. The design then gets sent electronically to the fab, where they make the mask using an electron beam - a little bit like how a CRT works, I believe, using electromagnets to steer the electrons. The mask actually looks very little like the design - today's circuits are measured in tens of nanometers, while the wavelength of the light that is used to pattern the design is in the hundreds of nanometers. So they do complex calculations using all the various optical distortions and interference and diffraction and whatever other effects there are, and work backwards from the desired design to find what the mask should look like to produce that design.

And hand-drawn can be better for a lot of reasons. Computers are great at following a set of rules, but what if you don't really know what the rules are, or how to express them? For example, how would you teach a computer to recognize a bicycle in a photograph? It can be done, but it takes a lot of training - and it's quite likely that it will pick up a lot of things that are not bicycles but look like them (perhaps a bicycle bumper sticker, or a piece of artwork), and it won't pick up bicycles that are different from what it was taught about (say a tandem or a recumbent). A human, on the other hand, will have no difficulty distinguishing a bicycle drawing from the real thing, or recognizing a new type of bicycle. So, at least for now, humans can still recognize optimizations that computers can't, and give it some guidelines to help improve the result. I'm sure much of that chip's layout was done with automated tools, but careful hand adjustments and hints to those tools can make a big difference in performance and power.

does this mean? (0)

Anonymous Coward | about 2 years ago | (#41457551)

That the cost of the new iphone is finally justified because of expensive handmade chips?

Re:does this mean? (1)

busyqth (2566075) | about 2 years ago | (#41457785)

That the cost of the new iphone is finally justified because of expensive handmade chips?

It's because of the gold connectors and diamond lenses.

Hand-drawn chips really better? (0)

Anonymous Coward | about 2 years ago | (#41457617)

Must mean that chip designing software is crap then. Should invest in better software?

(This post is half funny/half serious - it's 2012, haven't intel or amd engineers developed algorithms to do the chip design for them?

Re:Hand-drawn chips really better? (2)

busyqth (2566075) | about 2 years ago | (#41457757)

it's 2012, haven't intel or amd engineers developed algorithms to do the chip design for them?

No, they never thought of doing that. Hurry up and apply for the patent.

Re:Hand-drawn chips really better? (1)

espiesp (1251084) | about 2 years ago | (#41458391)

They probably haven't for the same reason that Intel or AMD engineers haven't developed algorithms to do whatever job you do for a living for you. Because computers aren't nearly as good at doing things as we sometimes give them credit for.

Layout by HAL (3, Informative)

Anonymous Coward | about 2 years ago | (#41457919)

" The question I have is how it's less expensive (in the long run) to lay a chip out by hand once instead of improving your VLSI layout software forever. NP classification notwithstanding."

I've done PCB layouts, microwave chip and wire circuits, as well as RFIC/MMIC layouts. Anyone who asks the question above has never done a real layout. Many autorouter and layout tools allow complex rules to match delays, keep minimum widths, etc. You can spend as much time on each layout trying to populate these rules for critical sections of a design, but it is like trying to train a 5 year old to do brain surgery. Digital design is rather much different than the analog circuits I work on, but you only have to do a few layouts of any flavor by hand in your life to be able to see just how scary it is to hand a layout to HAL.

Clearly autorouters and autogenerated layouts, and I don't mean to sound like too much of a luddite... I've witnesses plenty of awful hand layouts to go around as well.

Re:Layout by HAL (1)

taniwha (70410) | about 2 years ago | (#41458651)

well a cpu with a 1GHz clock has 1nS to process data between flops - yes it's a bit like laying out microwave stuff -but in the very small - what happens is that it all starts with some layout person/people creating a standard cell library, they'll use spice to simulate and characterise their results - they'll pass this to the synthesis/layout tool makes a good first guess, they'll add in some fudge factor - then a timing tool looks at the 3d layout and extracts real timing, including parasitics to everything in 3-space around a wire - they check - does the timing from every flop to every other flop through every possible path meet both setup and hold times for the destination flop - if it does you're golden, tape it out - if not tweak something or resynthsise a block with tighter constraints etc etc

There is very complex delay analysis done - in all corners of the underlying fab process - automated layouts seldom look "pretty" at least from the point of hand done boards

Apple... (0)

Anonymous Coward | about 2 years ago | (#41458015)

Seing those guys evolve is like watching an intricate ballet while everybody else is sumo wrestling.

Re:Apple... (2)

busyqth (2566075) | about 2 years ago | (#41458065)

Seing those guys evolve is like watching an intricate ballet while everybody else is sumo wrestling.

So are you calling Apple users effeminate?

ARM hard blocks are always laid out by hand... (4, Interesting)

Wierdy1024 (902573) | about 2 years ago | (#41458255)

When someone buys a design from ARM, they buy one of two things:

1. A Hard macro block. This is like an mspaint version of a cpu. it looks just like the photos here. The CPU has been laid out partially by hand by ARM engineers. The buyer must use it exactly as supplied - changing it would be neigh-on impossible. In the software world, it's the equivalent of giving an exe file.

2. Source Code. This can be compiled by the buyer. Most buyers make minor changes, like adjusting the memory controller or caches, or adding custom FPU-like things. They then compile themselves. Most use a standard compiler rather than hand-laying out the stuff, and performance is therefore lower.

The articles assertion that hand layout hasn't been done for years outside intel as far as I know is codswallop. Elements of hand layout, from gate design to designing memory cells and cache blocks have been present in ARM hard blocks since the very first arm processors. Go look in the lobby at ARM HQ in Cambridge UK and you can see the meticulous hand layout of their first cpu, and it's so simple you can see every wire!

Apple has probably collaborated with ARM to get a hand layout done with apples chosen modifications. I can't see anything new or innovative here.

Evidence: http://www.arm.com/images/A9-osprey-hres.jpg [arm.com] (this is a layout for an ARM Cortex A9)

Re:ARM hard blocks are always laid out by hand... (5, Informative)

Lunix Nutcase (1092239) | about 2 years ago | (#41458375)

When someone buys a design from ARM, they buy one of two things:

Which is not what Apple did.

Apple has probably collaborated with ARM to get a hand layout done with apples chosen modifications. I can't see anything new or innovative here.

No, they designed it themselves since they are an architectural licensee like Qualcomm. You remember how they bought PA Semi?

Really a work of art (0)

Anonymous Coward | about 2 years ago | (#41458401)

Ecce ARM.

And in other news... (0)

Anonymous Coward | about 2 years ago | (#41458919)

Apple has sued Chipworks for revealing company trade secret information, violating the terms of use attached to the device, and other intellectual property crimes.

Bundled in the Apple terms of use is an agreement not to reverse-engineer. They could not have obtained an Apple to deprocess without first agreeing to those terms.

Chipworks will belong to Apple when it is all over.

Load More Comments
Slashdot Login

Need an Account?

Forgot your password?