×

Welcome to the Slashdot Beta site -- learn more here. Use the link in the footer or click here to return to the Classic version of Slashdot.

Thank you!

Before you choose to head back to the Classic look of the site, we'd appreciate it if you share your thoughts on the Beta; your feedback is what drives our ongoing development.

Beta is different and we value you taking the time to try it out. Please take a look at the changes we've made in Beta and  learn more about it. Thanks for reading, and for making the site better!

IBM Reports Carbon Nanotube Chip Breakthrough

samzenpus posted about a year and a half ago | from the one-step-closer dept.

IBM 73

First time accepted submitter yawaramin writes "IBM has apparently made a breakthrough in arranging carbon nanotubes into the logic gates necessary to make a chip. This should help miniaturize and speed up processors beyond what today's silicon-based technologies are capable of. The article notes though that perfecting the carbon nanotube technology could take up the rest of this decade."

cancel ×
This is a preview of your comment

No Comment Title Entered

Anonymous Coward 1 minute ago

No Comment Entered

73 comments

enterprise (-1, Offtopic)

posthxc1982 (2539048) | about a year and a half ago | (#41802195)

here i come!

Re:enterprise (1)

gagol (583737) | about a year and a half ago | (#41802207)

Maybe it is my insomnia, but I really dont get what you are trying to communicate...

Re:enterprise (1)

posthxc1982 (2539048) | about a year and a half ago | (#41802247)

one step closer to Captain Bradley

Re:enterprise (-1)

Anonymous Coward | about a year and a half ago | (#41802569)

Bradley Manning?

Re:enterprise (0)

Anonymous Coward | about a year and a half ago | (#41803483)

Manning was a corporal. And corporals never amount to anything.

citation? (0)

Anonymous Coward | about a year and a half ago | (#41802229)

Can someone please provide a citation for the paper they published so I can read something with actual content?

Re:citation? (3, Interesting)

Anonymous Coward | about a year and a half ago | (#41802273)

Haven't found the actual paper, yet, but I think it's "High-density integration of carbon nanotubes via chemical self-assembly" as mentioned here: http://researcher.watson.ibm.com/researcher/view_pubs.php?person=us-aaronf&t=1 [ibm.com]

Re:citation? (1)

overmod (180722) | about a year and a half ago | (#41823345)

Slashdot effect seems to have killed this server temporarily -- HOLD OFF A FEW HOURS, FOLKS!

Re:citation? (4, Informative)

Dupple (1016592) | about a year and a half ago | (#41802405)

There's some info here on Nature but it's pay walled

http://www.nature.com/nnano/journal/vaop/ncurrent/full/nnano.2012.189.html [nature.com]

There's some additional info in a pdf from the same site here

http://www.nature.com/nnano/journal/vaop/ncurrent/extref/nnano.2012.189-s1.pdf [nature.com]

Re:citation? (2)

Khyber (864651) | about a year and a half ago | (#41810437)

If it's paywalled, don't even fucking bother to link it, most of us will naturally avoid the link.

If you can't find a non-paywalled version, then don't bother at all.

SPECS? (0)

Anonymous Coward | about a year and a half ago | (#41802587)

I just want to know what the specs are, like power consumption, clock speed, and FLOPs

Re:SPECS? (1)

NatasRevol (731260) | about a year and a half ago | (#41803561)

8, 5, 2.

I'm not giving you units, though.

Re:SPECS? (1)

Khyber (864651) | about a year and a half ago | (#41810457)

In order - Kilowatt-hours, decahertz, and kiloFLOPS.

Trying to hide the dismal performance of your company product? Perhaps you should be a bit more forthcoming, 'lest your NDA kill your company with your bullshit answer.

Re:SPECS? (0)

Anonymous Coward | about a year and a half ago | (#41819329)

No, Kilowatt-hours are energy, not power. And for the last number, the unit was already given in the question: FLOPS, not kFLOPS.

Re:SPECS? (1)

Khyber (864651) | about a year and a half ago | (#41830383)

power = energy, oh anonymous high school dropout.

kWh is power rate over time.

Please come back when you hold a certification or license to do electrical work.

Re:SPECS? (0)

Anonymous Coward | about a year and a half ago | (#41820735)

I see, you are using an unit-less measurement system. Must be Planck units. Thus using SI your specs are:

2.9*10^53 W, 9.3*10^43 Hz, 3.7*10^43 FLOPS

Now the clock speed and FLOPS are impressive, but I fear the power requirement is quite prohibitive.

Apparently? (0, Redundant)

hairyfish (1653411) | about a year and a half ago | (#41802243)

"IBM has apparently made a breakthrough..." They either have or haven't made breakthrough. "Apparently" doesn't really cut it I'm sorry.

Re:Apparently? (0)

Anonymous Coward | about a year and a half ago | (#41802275)

Do you know what "apparently" means? Unless the submitter was actually in the room when they made the breakthrough, it is the appropriate word to use.

Re:Apparently? (5, Funny)

K. S. Kyosuke (729550) | about a year and a half ago | (#41802703)

"IBM has apparently made a breakthrough..." They either have or haven't made breakthrough. "Apparently" doesn't really cut it I'm sorry

Well, at such a small scale, everything is controlled by quantum mechanics. Oh, excuse me: everything at such small scale may or may not controlled by quantum mechanics.

Re:Apparently? (1)

i (8254) | about a year and a half ago | (#41803997)

This is maybe a post. Maybe by me. Could be a good post ... or a bad.
(This was 3 quantbits.)

Re:Apparently? (1)

Dragonslicer (991472) | about a year and a half ago | (#41805891)

"IBM has apparently made a breakthrough..." They either have or haven't made breakthrough. "Apparently" doesn't really cut it I'm sorry.

It's not always immediately known if something will be a major breakthrough or not. If and when these chips come to market, we'll be able to look back and decide where the breakthroughs were.

Re:Apparently? (0)

Anonymous Coward | about a year and a half ago | (#41815347)

"IBM has apparently made a breakthrough..."

They either have or haven't made breakthrough. "Apparently" doesn't really cut it I'm sorry.

Well, they haven't yet determined if the crack they produced goes through the whole chip (i.e. a breakthrough) or only through parts of it.

How refreshing (4, Informative)

scdeimos (632778) | about a year and a half ago | (#41802245)

Most stories I see say that [insert favourite research here] will be ready for commercial production within five years. Finally, somebody's being honest and saying it won't be ready before the end of this decade.

Re:How refreshing (4, Insightful)

AbRASiON (589899) | about a year and a half ago | (#41802539)

Moderate you up or just type I agree? Too important to just mod, you're bang on point. After using the internet for over 15 years, definitely this is the case with tech articles. I think you could probably count the technological _huge_ leaps in the last 20 years on a single hand in regards to PC parts.

3D GPU stuff like 3DFX cards
SSD's
Ability to burn optical media
High speed internet
Flat panel displays

As for CPU speed increases, memory size increases, memory bandwidth increases, disk storage size increases - ALL of these have been slowly eeked out at a slow pace to keep the money flowing.

Re:How refreshing (1)

Nadaka (224565) | about a year and a half ago | (#41803563)

SSD's are not revolutionary. They are older than spinning magnetic disks, it just took them a lot longer to increase in speed and capacity compared to the first few generations of magnetic disks.

Re:How refreshing (1)

ShanghaiBill (739463) | about a year and a half ago | (#41803583)

... in the last 20 years ...

Ability to burn optical media

Sorry, but this didn't happen in the last 20 years. I bought my first CD-R writer in the fall of 1991 (21 years ago), and I think that they were on the market for about a year before that. If I recall correctly, the price was just under $8000.

Re:How refreshing (1)

justthinkit (954982) | about a year and a half ago | (#41804933)

Most of what you list is incremental. SSD over HD, really? Then why not mention SATA over ATA?
.

And how is a flat panel display a "huge" technological leap? Especially with LCD latency issues, LCD looks more like a downgrade, albeit a cheaper than CRT one.

"Ability to burn optical media" is as revolutionary as "buggy whip manufacture". I burn, on average, a disk or two per YEAR. At least you could have gone for USB thumb drives.

"High speed internet" is so "huge" a leap, it is not even needed for the low tech, text-based site we are discussing it on.

I was thinking more like:
Napster
Kazaa
Bit Torrent
Tor

Re:How refreshing (1)

Dog-Cow (21281) | about a year and a half ago | (#41808493)

You aren't really logical at all. SSD and HD (as in spinning media) are different technologies, with the former allowing for much greater speeds of data access. SATA vs ATA [sic] is just a change in interface. Both SSD and HDD can use the either, though I am not aware of any SSDs using (P)ATA.

LCD panels allow for smaller displays. They use less energy. You can fit one anywhere. Today's phones have better resolution than the desktop of 10 years ago. Try that with a CRT.

Being able to burn optical media was a huge deal. Before that, the most standard method of data interchange on physical media was the floppy. Just because it's (mostly) obsolete today has no bearing on its historical importance. That comment of yours is just you being a shithead.

Re:How refreshing (1)

Mashdar (876825) | about a year and a half ago | (#41810119)

I don't know. SATA vs ATA seems analagous to SSD vs HDD to me...

  • *In a black box, both pairs are roughly identical (in fact, SATA requires more adaptation from ATA than SSD from HDD),
  • *Both SATA and SSD are faster and fancier than their 1990s era brethren,
  • *SATA and SSD are really modern incarnations of much older technology coming back into vogue,
  • *And most importantly, SATA and SSD both begin with the letter S (crucial).

(PS I don't know why you wrote sic after ATA, since ATA was its original name.)

Re:How refreshing (2)

default luser (529332) | about a year and a half ago | (#41806725)

3D GPU stuff like 3DFX cards

No. There was nothing revolutionary about this. The progress was slow-and-steady like everything else.

You could already do fully-featured real-time 3D rendering for years before 3DFX cards were even conceived, and the price came down iteratively.

At first the only source for real-time 3D was government contractors with supercomputers. But this performance had a price (usually a million+)

Then the cost was reduced to the "thousands of dollars" over the next few years for arcades (and for major workstation vendors like SGI). This involved custom cores designed for that specific purpose (that were more efficient), and 1-2 die shrinks. Arcade games started with sprite scaling and rotation, or polygonal graphics in 1988, and scaled all the way up to games like Sega's Daytona USA (1993) featuring a texture-mapped and filtered immerse game world.

The cost was then reduced over the course of the next 4 years. In that time you had 1-2 silicon shrinks, allowing for greater integration. You also had the sudden appearance of the Pentium and Pentium Pro processors with strong floating-point performance, allowing for another cost reduction (temporary removal of the geometry unit from 3D chipsets).

In the end you got the 3DFX chipset (along with several other competing products), which was a result of 15 years of iterative progress.

Re:How refreshing (0)

Anonymous Coward | about a year and a half ago | (#41802751)

Finally, Area 51 Tech being released. Figuring out how clever aliens placed those carbon molecules is the tricky bit.
Maybe doping the ends with magnetic substance, magnetising, gluing them in place, then using acid or alien spit to wash away the metallic positioners, then a laser to burn traces between the upright and aligned fibers.

Re:How refreshing (1)

Sulphur (1548251) | about a year and a half ago | (#41805731)

Finally, Area 51 Tech being released. Figuring out how clever aliens placed those carbon molecules is the tricky bit.
Maybe doping the ends with magnetic substance, magnetising, gluing them in place, then using acid or alien spit to wash away the metallic positioners, then a laser to burn traces between the upright and aligned fibers.

Borrow from nature and use a jig to place parts like making proteins.

--

Chief, the ram is left handed and the fpga is right handed. What shall we do?

Re:How refreshing (1)

K. S. Kyosuke (729550) | about a year and a half ago | (#41803383)

Most stories I see say that [insert favourite research here] will be ready for commercial production within five years. Finally, somebody's being honest and saying it won't be ready before the end of this decade.

Which is a shame, because we will need those powerful computers to crack the secret to controlled nuclear fusion, which, *after* getting those computers, will only be twenty years away!

Re:How refreshing (1)

interkin3tic (1469267) | about a year and a half ago | (#41810297)

My impression is that the "5 years" can be read "It's not available right now, there are some other barriers to this being marketed that I don't work on, it's anyone's guess as to how long that will take, but everyone will keep asking us how long until it's available unless we throw out a number so five is close enough to let you know you should remain interested but not so close that you'll expect it next year."

It's the marketing types, the reporters, and the audience of the news that demand the 5 year predictions, the researchers and engineers don't know, but we wouldn't be happy with "It will get here when it fucking gets here."

URL for the IBM research paper and press release (5, Informative)

aheath (628369) | about a year and a half ago | (#41802265)

The IBM research paper is available at http://www.nature.com/nnano/journal/vaop/ncurrent/full/nnano.2012.189.html [nature.com] The paper is protected by a paywall.

The IBM press release is available at http://www-03.ibm.com/press/us/en/pressrelease/39250.wss [ibm.com]

I recommend reading the comments on the New York Times article. My favorite comment so far is:

MC - NYC
The Singularity edges closer...

Re:URL for the IBM research paper and press releas (3, Funny)

Anonymous Coward | about a year and a half ago | (#41802289)

Can't wait for marketing to get involved, changing high-density carbon nanotube transistors (CNTs) into carbon ultra-nanotube transistors.

Re:URL for the IBM research paper and press releas (2)

aheath (628369) | about a year and a half ago | (#41802329)

IBM marketing will never approve a 4 letter acronym when a 3 letter acronym will suffice. ( Deadpan humor mode set on full. )

Re:URL for the IBM research paper and press releas (4, Informative)

Anonymous Coward | about a year and a half ago | (#41802339)

article text:
Carbon nanotubes have potential in the development of high-
speed and power-efficient logic applications1–7. However, for
such technologies to be viable, a high density of semiconduct-
ing nanotubes must be placed at precise locations on a sub-
strate. Here, we show that ion-exchange chemistry can be
used to fabricate arrays of individually positioned carbon nano-
tubes with a density as high as 1 3 109cm22—two orders of
magnitude higher than previous reports8,9. With this approach,
we assembled a high density of carbon-nanotube transistors in
a conventional semiconductor fabrication line and then electri-
cally tested more than 10,000 devices in a single chip. The
ability to characterize such large distributions of nanotube
devices is crucial for analysing transistor performance, yield
and semiconducting nanotube purity.
The precise placement of carbon nanotubes on a substrate typi-
cally involves one of three techniques: the direct growth of nano-
tubes on a substrate10,11, the transfer of nanotubes from a ‘growth’
substrate to a device substrate5,6, or the deposition of nanotubes
from solution onto a device substrate8,9,12–18. Because nanotubes
can be metallic or semiconducting, a further consideration for
high-performance digital logic is the degree to which metallic nano-
tubes can be eliminated. Although approaches for enriching sub-
strate-supported semiconducting nanotubes during or after
synthesis have been demonstrated19,20, currently the most effective
techniques involve processing the nanotubes in solution21.
One promising approach for placing solution-based nanotubes is
to selectively position them on a specific substrate by chemically
functionalizing the nanotubes or the substrate14–18. This typically
involves using a patterned surface (such as SiO2/HfO2) such that
nanotubes deposited from solution adhere only to one part of the
pattern (the HfO2, for example). Key metrics for determining
the efficacy of the deposition are the density of individually
placed nanotubes, which must exceed 1 × 1010cm22, with a pitch
smaller than 10 nm for high-performance logic6,7, and the selectiv-
ity, which is the degree to which adsorption takes place only on the
pattern of interest. In general, however, solution-based approaches
that result in high density exhibit poor selectivity14,16, and those
that offer high selectivity have low density17,18.
We have developed a selective placement method based on ion
exchange between a functional surface monolayer and surfactant-
wrapped carbon nanotubes in aqueous solution. Strong electrostatic
interaction between the surface monolayer and the nanotube surfac-
tant leads to the placement of individual nanotubes with excellent
selectivity and a density of 1 × 109cm22. Furthermore, the
approach is compatible with the most efficient solution-based sep-
aration schemes21, allowing wafer-scale integration using highly
purified carbon nanotubes.
Our nanotube placement using an ion-exchange technique
is illustrated in Fig. 1a. The surface monolayer is formed from
4-(N-hydroxycarboxamido)-1-methylpyridinium iodide (NMPI)
molecules, which were synthesized from commercially available
methyl isonicotinate (see Methods). The monolayer contains a
hydroxamic acid end group that is known to self-assemble on
metal oxide surfaces, but not on SiO2(refs17,18,22). We selectively
self-assembled NMPI on HfO2regions of a patterned SiO2/HfO2
surface. The functionalized surface was then placed in an aqueous
solution of carbon nanotubes. Solubility of the nanotubes was
achieved using an anionic surfactant (sodium dodecyl sulphate,
SDS). Excess surfactant in the solution was removed by dialysis.
The anion of NMPI (that is, iodide) is exchanged with the
anionic surfactant wrapped around the nanotubes, leading to a
strong coulombic attraction between the negatively charged surfac-
tant and the positively charged monolayer. In this process, the
iodide of the monolayer and the sodium ion of the surfactant are
removed as sodium iodide, which is dissolved into the solution.
The exchange mechanism was verified using X-ray photoelectron
spectroscopy (XPS) measurements made before and after exposure
of the monolayer to the surfactant (Supplementary Fig. S1).
To assess the selectivity and density of this placement technique,
arrays of long, narrow HfO2trenches were fabricated on a SiO2sub-
strate. Carbon nanotubes were selectively depositedon HfO2regions
coated by NMPI (see Methods). Scanning electron microscopy
(SEM) and atomic force microscopy (AFM) images recorded after
nanotube deposition are shown in Fig. 1b–d. On the larger, open
HfO2areas (Fig. 1b), the deposited nanotubes are well dispersed
and form monolayers with extremely high density and excellent
selectivity. High density and selectivity are maintained even in the
narrower trenches (200 nm, Fig. 1c,d).
When positioning nanotubes on a substrate, it is critical to be
able to control their alignment in addition to their location.
Angular misalignment leads to a corresponding variation in the
nanotube channel and contact lengths of transistors fabricated
with the nanotubes, resulting in unacceptable variation in device
performance. Achieving high selectivity in the present approach
not only ensures accurate location positioning, but also promotes
alignment of the nanotubes along a trench. Figure 2a shows how
the alignment improves as the trench width (Wtr) is reduced. By
reducing Wtrto 70 nm, the angular variation of the nanotubes rela-
tive to the trench axis is reduced to less than+308. Figure 2b shows
nanotubes selectively placed in an array of 70-nm-wide HfO2
trenches with 200 nm pitch.
While placement in long, narrow lines is useful forcharacterizing
alignment and density, device applications require precise confine-
ment of nanotubes in both dimensions, that is, on narrow and short
lines. Figure 2c presents an SEM image of nanotubes deposited
onto an array of short and narrow trenches with 200 nm pitch in
the x direction and 500 nm pitch in the y direction, corresponding
to a density of 1× 109sites cm22. This density represents an
improvement of two orders of magnitude over previously reported
results obtained using microcontact printing8, dielectrophoresis9
or a scanning probe12. As determined from more than 350 trench
images, the placement yield was ?90% (that is, 90% of the trenches
contained at least one nanotube). However, a more comprehensive
yield can be evaluated by measuring the electrical properties (for
example, resistance) of transistors fabricated on the placed nano-
tubes; for the transistor to work, the nanotube must be properly
positioned in the trench so as to span the defined source and
drain electrodes.
This ability to accurately place individual, aligned nanotubes at a
high density enables the fabrication of a large number of nanotube
transistors on a single chip. Using the placement method, we fabri-
cated thousands of transistors with a channel length (spacing
between source and drain contacts) of 100 nm. As estimated from
SEM images of the channel regions, the average number of nano-
tubes per channel was dependent on the trench dimensions
and the concentration of nanotubes in the deposition solution; nar-
rower trenches and more diluted nanotube solutions resulted in
a larger fraction of single-nanotube transistors (up to ?78%;
SupplementaryFig. S3).Direct numericalsimulation ofthe measured
distributions of nanotubes per channel suggests that the probability
of a nanotube from solution adhering in an empty trench is
roughly three times higher than that of adhering in an occupied
trench (Supplementary Fig. S4). This propensity to form single-
nanotube trenches is an important advantage of this approach.
Figure 3a presents images of the channel regions of an array of
nanotube transistors with a device pitch of 300 nm—an order of
magnitude smaller than previous reports (?5 mm)9. Each transistor
contained one trench of width 100, 150 or 200 nm and length 1 mm.
Because the nanotubetransistors were designed and fabricated using
a conventional semiconductor fabrication facility, characterization
of the devices was compatiblewith high-volume electrical character-
ization tools, enabling rapid testing of thousands of devices. Plots of
drain current (ID) versus gate voltage (VG) from a subset of devices
on a chip (?300 devices) are shown in Fig. 3b. The curves provide
valuable insight into the variation that exists in the nanotube tran-
sistors, in addition to the population of devices that contained a
metallic nanotube. A device yield of .90% was obtained with
150 nm and 200 nm trench widths; as the trench width decreases,
the yield of semiconducting devices increases, which is attributed
to the yield of single-nanotube devices increasing (Supplementary
Fig. S5). The highest device yield was achieved after optimizing
the surface-cleaning step that takes place before deposition of the
NMPI monolayer; in other words, the density of NMPI, and thus
nanotube density, is dependent on the surface cleanliness.
For fast assessment of the key device parameters from a large
number of devices, the measured characteristics for each transistor
were modelled by fitting the measured ID–VGcurves to a parametric
function (see Methods). Representative curve fits are shown in
Fig. 3c. Figure 3d shows the distributions of the threshold voltage
(VT) and inverse subthreshold slope (SS) extracted from 7,066 semi-
conducting devices. These devices were selected from about 12,000
connected nanotube devices by excluding devices that did not
exhibit current levels expected for the transistor dimensions, and
so on (such devices typically contained a metallic nanotube or
an extremely short contacted length, leading to high contact resist-
ance and low current5). In this analysis, VTwas defined as the
gate voltage corresponding to a drain current of 3 nA. The
average on-state drain current (Ion), measured at VG¼VT2 1.5 V
and VDS¼ 20.5 V, was 1.33 mA. These results show that the per-
formance of devices fabricated using the chemical assembly is com-
parable to that produced by the deposition of nanotubes from
solution that did not undergo the same chemical treatments23–25.
Annealing the wafer after nanotube deposition to remove the
NMPI monolayer is crucial to maintaining this good electrical per-
formance (Supplementary Fig. S6).
Before this study, device metrics for nanotube transistors, such as
Ion, VT, SS and the purity of semiconducting devices, were typically
evaluated from, at most, a few hundred devices23–27. However, to
realistically consider carbon-nanotube transistors for a technology,
the distribution in performance across tens of thousands of
devices must be statistically analysed and optimized. One key
example comprisesthe accurate measurement of the fraction of met-
allic nanotubes in a solution. Metallic nanotubes lead to transistor
‘shorts’, and must be largely eliminated. A competitive carbon-
nanotube logic technology requires an extremely high purity of
semiconducting devices, with a metallic fraction less than at least
1× 1024. Measuring this level of purity in solution has not
proven possible, leaving large-scale device fabrication and testing
as the only viable method. Our new ion-exchange placement
approach provides a platform for such testing to be realized.
The capability of measuring the device parameter distributions
from a large number of nanotube transistors will also be critical
in developing robust wafer-scale processes for carbon-nanotube
integrated circuits.
In summary, we have demonstrated a new ion-exchange surface
chemistry approach for the placement of individual carbon nano-
tubes with a density of 1 × 109cm22. The method combines excel-
lent selectivity with nanotube alignment at a high density to enable
the formation of single-nanotube devices. The compatibility of this
approach with existing semiconductor technology was shown by
fabricating tens of thousands of nanotube transistors within a con-
ventional fabrication facility. Electrical testing shows that the per-
formance of nanotube devices is not significantly degraded by the
deposition chemistry. This new placement technique is readily
implemented, involving common chemicals and processes, and
provides a platform for future nanotube transistor experimental
studies. Furthermore, these results show that nanotube placement
via chemical self-assembly is a promising approach for developing
a viable carbon-nanotube logic technology compatible with existing
semiconductor fabrication.
Methods
Synthesis of NMPI molecules. The surface monolayer was formed from NMPI
molecules, and was synthesized in two steps from the commercially available
methyl isonicotinate. Methyl isonicotinate was converted to its corresponding
hydroxamic acid, 4-(N-hydroxycarboxamido)pyridine, using a previously described
procedure in ref. 28. Methyl iodide (10 g) was added to a solution of 4-(N-
hydroxycarboxamido)pyridine (5.14 g, 0.03 mol) in 200 ml of methanol, and the
mixture was stirred at room temperature for 3 days. The precipitate was filtered
and washed with methanol and dried. Crystallization from 9:1 ethanol–water
afforded the analytically pure pyridinium compound NMPI as light yellow
crystals (7.35 g, 84%).1H NMR (DMSO-d6), d; 4.38 (s, 3H), 8.3 (d, j ¼6 Hz, 2H),
9.1 (broad d, j ¼ 6Hz, 2H).
Purification of single-walled carbon nanotubes. A 1 g ml21solution of carbon
nanotubes (Hanhwa Nanotech) in 1% aqueous SDS (Sigma Aldrich) was prepared
via horn sonication (99%, 1 s pulse, 20 min). The solution was then purified using a
step-gradient ultracentrifugation process. For the purification, 6 ml of 1% SDS in
45% iodixdinol (Sigma Aldrich) solution was prepared and layered below 6 ml of the
nanotube solution in a 12 ml centrifuge tube. The layered solution was then
centrifuged for 15 h at 41,000 r.p.m. using a Beckman Coulter Optima L-100 XP
ultracentrifuge equipped with a swinging bucket-type rotor. The purified nanotube
solution sedimented at the interface of the two layers while the graphitic impurities
and large bundles settled to the bottom of the centrifuge tube. The purified nanotube
solution wasthen removed via pipette and diluted 1:1 with 1% aqueous SDS solution
before loading on the column. It is important to note that this step-gradient
centrifugation step is only used to remove the graphitic impurities and concentrate
the solution (very effective) and does not sort the nanotubes in any fashion. A
chromatography step was then performed to isolate the semiconducting nanotubes.
Isolation and dialysis of semiconducting-enriched carbon-nanotube solution.
The semiconducting nanotubes were separated from the purified nanotube solution
by means of column chromatography, which was modified from a previously
reported method described in ref. 29. A column was prepared by loading a 25-mm-
diameter glass chromatography column with a Sephacryl-200 slurry (Sigma
Aldrich). The column was flushed with 1% wt/vol SDS solution several times. The
nanotube solution was then added to the column and allowed to pass through the
column using a small positive nitrogen gas pressure. Once the solution was fully
inserted into the column, more 1% SDS solution was added and was continually
added until all of the nanotubes (now separated) passed through the column.
Initially, a blue fraction (metallic) passed through, followed by a red band
(semiconducting). Fractions of the solution were collected in small glass vials and
characterized using a UV–vis–NIR absorption spectrometer (Perkin Elmer Lambda
950). Excess SDS in the solution was removed via dialysis, with the concentrated
nanotube solution syringed into a dialysis cartridge and placed in 1 l of deionized
water and changed daily for four days.
Fabrication of carbon-nanotube transistors. To assemble the carbon nanotubes,
HfO2trenches were fabricated by patterning SiO2on HfO2-coated substrates. First,
  HfO2was deposited on a highly doped p-type silicon substrate via chemical
vapour deposition (precursor, hafnium-tetra-tert-butoxide Hf(C4H9O)4; carrier gas,
O2; working pressure/temperature, 0.3 torr/500 8C) and treated by a rapid thermal
annealing at 700 8C in a N2atmosphere. Trench patterns were defined by electron-
beam lithography (in PMMA), deposition of 5 or 10 nm of SiO2by electron-beam
evaporation with a deposition rateof 0.2 nm s21, and liftoff in acetone. Note that the
role of the evaporated SiO2layer was to prohibit the deposition of nanotubes so as to
achieve the demonstrated excellent selectivity, and the layer was not included in the
gate dielectric of final devices. Before self-assembly of the NMPI monolayer, the
substrate was cleaned by oxygen plasma at 300 mtorr for 5 min. The NMPI
monolayer was then assembled on the patterned surface by placing the substrate in a
3.5 mM solution of NMPI (3:1 ethanol/water) for 1 h. The surface was then rinsed
with ethanol. The substrate was then placed horizontally with its surface facing
upwards in the dialysed nanotube solution for 1 h, without an agitation. After
nanotube deposition, the substrate was rinsed with flowing deionized water for 30 s
and subsequently in a sonication bath with deionized water for 1 min. The substrate
was then annealed at 450 8C under Ar/H2for 5 min to drive off the monolayer and
eliminate its effects on device performance. Source and drain electrodes
(Ti/Pd/Au ¼ 0.5/20/20 nm) were patterned on the nanotubes via electron-beam
lithography with achannel length of 100 nm. The highly doped silicon substratewas
used as a backgate. In the deposition process, an effective cleaning process was
critical to achieve a high density of placed nanotubes. The majority of the electrical
characterization for large device sets in this work was performed on wafers that had
been cleaned with a 700 8C anneal in oxygen before NMPI deposition. However, this
process only provided adeviceyield of ?50%.A subsequent wafer thatwas subject to
the oxygen plasma cleaning step resulted in the ?90% yield.
Fitting measured VG–IDcurves. The measured data from large sets of devices were
automatically analysed by fitting each measured curve to the expression
ID(VG) = Ioff+ aln(1 + z) + b
z
1 + z
where z ¼ exp[(VT–VG)/SS]. The five fitting parameters are VT, Ioff, SS, a and b. Ioff
is the off-state drain current defined as ID(VT 1 V). This strictly empirical fitting
function includes all the necessary features to allow a good fit and analysis: a small
off-state current, a voltage threshold and an exponential rise near the threshold.

Thank you! (1)

Okian Warrior (537106) | about a year and a half ago | (#41806329)

Thank you!

I don't know how many times I've wanted to read a paper mentioned here that's essentially unavailable.

I think your method of cut/paste the text strikes a good compromise between giving out the information and preventing unauthorized copy. The information is available to motivated readers, but can't easily dilute the journal's copyright. A truly interested reader could then pay for the actual article from the Journal.

Keep up the good work, whoever you are.

Re:Thank you! (1)

tehcyder (746570) | about a year and a half ago | (#41815691)

I think your method of cut/paste the text strikes a good compromise between giving out the information and preventing unauthorized copy.

You seriously don't think that copying and pasting the whole text of a work constitutes copyright infringement?

I'm not a fan of paywalls for research papers, but you can't just magic them away.

Re:URL for the IBM research paper and press releas (0)

Anonymous Coward | about a year and a half ago | (#41806785)

Is all that babble about the 'singularity' serious, or just ironic posturing?

Does MR. 'MC', who posted "The Singluarlity edges closer...", really believe that IBM's efforts are a step towards greater-than-human superintelligence? Or is it like so much zombie-preparation: ironic overemphasis of the dangers for comic effect (with the secondary effect of assuaging real fears about the future-unknown in these somewhat-more-than-usually uncertain times)?

It's a small breakthrough (1)

Anonymous Coward | about a year and a half ago | (#41802493)

of interconnected tubes

Internet (0)

Anonymous Coward | about a year and a half ago | (#41802597)

So the internet may turn out be a bunch of interconnected tubes after all?

premature optimization postponed (5, Interesting)

epine (68316) | about a year and a half ago | (#41802649)

A failure to increase performance would inevitably stall a growing array of industries that have fed off the falling cost of computer chips.

Actually, no. Micro-architecture could continue to evolve without die shrinks (likely toward a proliferation of specialized units) and software could also evolve. Probably both for a decade or so, before the shrink stall becomes a fed stall. A feature of Moore's Law rarely expressed is that software lags architecture, and architecture lags die size.

I realized a long time ago that if I could gain a 50% speed increase by rewriting a critical application loop in assembly language, it generally wasn't worth the bother. The next processor architecture would mess up you clever clock-count calculations. The effort was almost always better invested in satisfying feature demand as PCs became more capable. Not only does the architectures improve, but so does the cleverness of your compiler (not including your hand-polished asm). If the software people actually knew that die shrinks were a thing of the past, it would make sense to be more aggressive in the choice of algorithms and execution regimes. They might even be well paid to indulge in premature optimizations postponed, since this would become the main avenue to sustaining performance gains.

There might be more pressure to bet on the right horse, which could thin the herd. Competence gradients tend to have this effect.

Re:premature optimization postponed (1)

Belial6 (794905) | about a year and a half ago | (#41806015)

This is correct. It is why I have always argued that 'Software Bloat' is not a problem. $10,000 spent on optimizing a piece of code is a worse investment than spending $2000 on writing another piece of 'bloated' code that optimizes your business and makes you $10,000s more in profit. All the while having the steady march of hardware development both make all of the code faster, as well as reduce the value of any previous optimizations.

If and when we hit a wall on hardware speed, then we can spend the next few decades on optimization.

Re:premature optimization postponed (1)

rdnetto (955205) | about a year and a half ago | (#41810755)

There's a difference between premature optimization and software bloat. I can see absolutely no reason one program should take up 2+ orders of magnitude more resources than a competing product with 90% of the features.

What A Load Of Bull (0)

Anonymous Coward | about a year and a half ago | (#41806241)

If all software were made as clunky and bloated as typical M$ software, we would not have smart phones that last longer than one hour, we would not have lightning fast search engines.

If we would use lead to make A380s, one aircraft could fly every other week; propelled by Saturn V engines. But who cares ? In the future we will have nuclear engines and we can actually have Lead Planes For Everyone !!!!

The Logic Of American Waste.

Re:What A Load Of Bull (0)

Anonymous Coward | about a year and a half ago | (#41830653)

I think of optimization like a supercar. I can either start replacing bits of the frame with carbon fiber at clever engineering to make it faster/better endurance (fuel effeciency is worth it's weight in gold in a race), or I can use better engineering in the engine to make it better at using less gas and creating more horsepower and torque.

in computers, there is not much of a point in making the body lighter because you get a much better return on investment by going with engine (hardware) design because it only takes a year or so to get an extra 50 HP from the same size, weight, and cost engine.

IBM will do nothing but patent troll it (-1)

Anonymous Coward | about a year and a half ago | (#41802715)

IBM will just patent this and do nothing but wait till someone solves all the million other problems associated with this, then take all their money.

Welcome to the patent world. Where companies research things, not to solve all the problems and make stuff, but to solve one or two problems likeliest to be infringed on, and then wait for companies to actually try to make the thing and sue them.

They're researching better batteries too. No intention of ever making batteries, but as we switch to electric cars, batteries will be an important place to lay a patent landmine.

Re:IBM will do nothing but patent troll it (2)

bws111 (1216812) | about a year and a half ago | (#41802805)

Do you have any evidence of IBM doing this? Ever?

Re:IBM will do nothing but patent troll it (0)

Anonymous Coward | about a year and a half ago | (#41803157)

Do you have any evidence of IBM doing this? Ever?

You mean, IBM betting on the right horse? Never.

Can you name the converse? (0)

Anonymous Coward | about a year and a half ago | (#41803877)

Can you name the converse? They were granted nearly 3000 patents in year 2000 alone, perhaps you can name 10 of them used by IBM to actually make and sell things? Just 10 out of those 3000 patents would do.

Re:Can you name the converse? (1)

bws111 (1216812) | about a year and a half ago | (#41804125)

I am not about to search for IBMs patents and then tell you where there are used, that is just pointless. But you would have to be a complete idiot to think that there is nothing patented in their new z12 mainframes, or Power 7 systems, or the new Pure Systems stuff. Then there are the chips themselves which no doubt have many patented things (including manufacturing processes). And their systems manufacturing processes probably have patented elements. Then of course there is their software.

OK, I'll help you (0)

Anonymous Coward | about a year and a half ago | (#41804573)

I chose 2000 because its a round number and 12 years is long enough for them to get a product out the door. Lets take their star patent the one they marketed with the announcement of getting most patents, the micro inductor on silicon one.

I'm guessing from a patent search its this one, although it seems to pop up as 1999,2000,2002, with minor variations.
http://www.google.com/patents/US5884990

Let identify what the invention is there. Perhaps it's coils on silicon? That way of fabricating the microcoil looks clever? Nope, that's Texas Instruments from 1973
www.google.com/patents/US3881244

So what did they invent there? Buggered if I know, seems to be laying them out in a loop so they occupy smaller space on the die?

"I am not about to search for IBMs patents and then tell you where there are used"
If you're not prepared to search patents, just search Slashdot

http://slashdot.org/story/10/11/25/0416208/coder-accuses-ibm-of-patenting-his-work
Man creates heapcheck lib to guard against heap overflow attacks, IBM patents his work IN AN OS. As if bundling in the OS actually constitutes an inventive step.

http://yro.slashdot.org/story/12/01/10/1450255/ibm-snags-patent-on-half-day-off-of-work-notifications
IBM patents 'portion of a day' busy notifications. (seriously USPTO, seriously?)

http://idle.slashdot.org/story/09/12/30/166220/uspto-awards-lol-patent-to-ibm
IBM patents LOLs, seriously???

They're a troll, they patent derivations of others inventions and keep re-patenting them with minor tweaks, they are the worlds biggest patent troll. A cleverly marketed on, I'll give you that, but a troll nevertheless.

Re:IBM will do nothing but patent troll it (1)

overmod (180722) | about a year and a half ago | (#41823515)

Perhaps not, but I CERTAINLY remember what happened to the Peanut in order to satisfy the Displaywriter people. Semantically there is little difference to me who the gatekeepers who restrict development actually call themselves... when the result is suppression of the fruits of applied technology.

A step in the right direction (1)

ozduo (2043408) | about a year and a half ago | (#41802755)

Although if they had used unobtanium that would be the ultimate.

Take up the rest of this decade? (0)

Anonymous Coward | about a year and a half ago | (#41802797)

What, all of it? I've got a lot on my plate already you know.

But when will they stop... (-1)

Anonymous Coward | about a year and a half ago | (#41802931)

Helping the Third Reich kill Jews?

IBM is pure evil.

Another amazing breakthrough from IBM... (1)

sethmeisterg (603174) | about a year and a half ago | (#41809321)

...that'll take another few decades to realize. They're really awesome about tooting their own horns. Execution? Not so much.

obligatory XKCD (0)

Anonymous Coward | about a year and a half ago | (#41839767)

http://xkcd.com/678/

Check for New Comments
Slashdot Account

Need an Account?

Forgot your password?

Don't worry, we never post anything without your permission.

Submission Text Formatting Tips

We support a small subset of HTML, namely these tags:

  • b
  • i
  • p
  • br
  • a
  • ol
  • ul
  • li
  • dl
  • dt
  • dd
  • em
  • strong
  • tt
  • blockquote
  • div
  • quote
  • ecode

"ecode" can be used for code snippets, for example:

<ecode>    while(1) { do_something(); } </ecode>
Sign up for Slashdot Newsletters
Create a Slashdot Account

Loading...