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Tiny Chiplets: a New Level of Micro Manufacturing

Soulskill posted about a year ago | from the website-idea:-chiplets-&-diplets dept.

Hardware 83

concealment sends this quote from the NY Times: "Today’s chips are made on large wafers that hold hundreds of fingernail-sized dies, each with the same electronic circuit. The wafers are cut into individual dies and packaged separately, only to be reassembled on printed circuit boards, which may each hold dozens or hundreds of chips. PARC researchers have a very different model in mind. ... they have designed a laser-printer-like machine that will precisely place tens or even hundreds of thousands of chiplets, each no larger than a grain of sand, on a surface in exactly the right location and in the right orientation. The chiplets can be both microprocessors and computer memory as well as the other circuits needed to create complete computers. They can also be analog devices known as microelectromechanical systems, or MEMS, that perform tasks like sensing heat, pressure or motion. The new manufacturing system the PARC researchers envision could be used to build custom computers one at a time, or as part of a 3-D printing system that makes smart objects with computing woven right into them."

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Seems unreliable (0)

Anonymous Coward | about a year ago | (#43407705)

And computers must be reliable?

Can laser printing create nano-size circuits ? (1)

Taco Cowboy (5327) | about a year ago | (#43407765)

Many chips that we are using today are fabricated with circuit lines that are really really tiny, to the point of nano-meter wide

For example, the latest Intel's microchip, the Ivy Bridge (and soon the Haswell) have circuit-sizes as small as 22nm

Can the PARC's laser printer churn out chips with similar nano-meter size circuits?

Re:Can laser printing create nano-size circuits ? (1)

femtobyte (710429) | about a year ago | (#43407923)

I'm guessing they didn't just hack this together from a broken LaserWriter II. They can basically use the same UV laser optics technology that regular lithography systems use to make "normal" chips. I doubt they'd start at the very bleeding edge 22nm process, but lots of chips are made far more coarsely than that.

Re:Can laser printing create nano-size circuits ? (2)

viperidaenz (2515578) | about a year ago | (#43408291)

A Laser printer doesn't use the same technology to make "normal" chips. A laser is used to create a static charge on a drum that picks up toner and rolls it on to the paper. From their likening it to a laser printer, I'm assuming they're picking up "chiplets" instead of toner with a drum.

Nothing like the process of burning away or curing a resist material then chemically removing exposed areas that is used to make "normal" chips.

Re:Can laser printing create nano-size circuits ? (2)

Dogtanian (588974) | about a year ago | (#43411125)

From their likening it to a laser printer, I'm assuming they're picking up "chiplets" instead of toner with a drum.

You're only assuming and guessing though... but that's not really your fault, because the article didn't explain any of this. Am I the only person that found it disappointing in terms of describing how *exactly* the process was supposed to work, rather than making generalised comparisons with a laser printer? A laser printer simply has to deposit a certain amount of a homogenous material in a given position, whereas this would have to deposit a specific component type (of a mixture) at a given location, and this major difference isn't addressed.

The closest it came to this was describing "microscopic electrical fields [that] control the precise placement of tiny electronic circuits — not just in the correct position, but with the proper orientation as well", but without saying how this was meant to work.

Re:Can laser printing create nano-size circuits ? (1)

viperidaenz (2515578) | about a year ago | (#43415849)

It describes the chiplets being suspended in a liquid.
My assumption is they use the electrical field to position the chiplet in the correct place and orientation before being picked up and rolled on to the substrate.

It's that or they splash a bunch of this liquid containing the chiplets on the substrate then position them using the electrical fields. I imagine they'd want to use reasonable force to push them down to make proper contact with the traces. Otherwise you'd have to do the whole wiring bonding thing and it becomes nothing more than small scale chip on board. Good luck building your wire bonding robotic arm to operate reliably and at speed at the scales they're talking about

Re:Can laser printing create nano-size circuits ? (0)

Anonymous Coward | about a year ago | (#43412975)

LOL, no.

A lithography machine, "scanner", is easily one of the most expensive and complex piece of manufacturing machine available to man today. The next generation EUV machines are expected to cost $150M each. And that is just for a single machine that churns out maybe 100 wafers per second. Mind you, each wafer has to go through 20-30 lithography steps.

Re:Can laser printing create nano-size circuits ? (1)

Khyber (864651) | about a year ago | (#43408713)

"For example, the latest Intel's microchip, the Ivy Bridge (and soon the Haswell) have circuit-sizes as small as 22nm"

I'll bet on the traces being even smaller than that. You must mean transistor size.

Re:Can laser printing create nano-size circuits ? (1)

WhiteDragon (4556) | about a year ago | (#43431215)

"For example, the latest Intel's microchip, the Ivy Bridge (and soon the Haswell) have circuit-sizes as small as 22nm"

I'll bet on the traces being even smaller than that. You must mean transistor size.

It means feature size. A feature can be part of a transistor, or a circuit trace, or a bunch of other things.

Re:Can laser printing create nano-size circuits ? (0)

Anonymous Coward | about a year ago | (#43410061)

They're using the laser to place the (conventionally made) chiplets, not make the chiplets.

Just so you know (1)

Osgeld (1900440) | about a year ago | (#43407835)

They do put other things in chips besides just computer components

Re:Just so you know (3, Funny)

kelemvor4 (1980226) | about a year ago | (#43408033)

I like cool ranch flavoring myself.

Re:Just so you know (2)

Neil Boekend (1854906) | about a year ago | (#43409831)

Yes, such things as salt, paprika flavor (or cheese and union). It makes for far more tasty chips.

Re:Just so you know (1)

Guppy (12314) | about a year ago | (#43411961)

They do put other things in chips besides just computer components

This. ^

I doubt you'll be seeing this on your desktop CPU, where everything can be banged out in the same fab. But suppose it were some telecom specialty chip, you could combine Silicon Carbide Chiplets with Germanium Chiplets with Laser Chiplets, all from different manufacturers.

I bet toner&drum replacment will cost a bundle (0)

Anonymous Coward | about a year ago | (#43407857)

...and the recycled refills will look crappy.

quality (1)

serbanp (139486) | about a year ago | (#43407879)

of the weed they're smoking here at PARC in Palo Alto must be really good. It allows them to dream wide-open-eyed, glossing over showstoppers such as reliability and poor cost structure.

What next? Tiny chiplet sections assembled to create tiny chiplets, then the ultimate goal of assembling components one atom at a time?

Re:quality (1)

Anonymous Coward | about a year ago | (#43407971)

There are already services like MOSIS to help low volume chip orders cut cost by essentially making a multi-tenent wafer in one fab run. Instead of having the customer buying a single prototype chip pay for a whole wafer's worth of processing, they each pay a part. It's like freight consolidators for container ships.

A completely separate issue is processor-in-memory fab techniques. It turns out that the most efficient logic and RAM fabs use different physics to produce their electrical components on the wafer. Making a combined logic and memory wafer requires detuning the process to be less optimal for one or both of these functions. So unless they can also come up with an inkjet like process to change process chemistry on minute parts of the wafer, they will run into the same cost issues as all other process-in-memory researchers.

diffrent chiplets manufactured separately,methinks (3, Insightful)

girlinatrainingbra (2738457) | about a year ago | (#43408053)

re: unless they can also come up with an inkjet like process to change process chemistry on minute parts of the wafer, they will run into the same cost issues as all other process-in-memory researchers.
.
I believe that the different substrates used in the printer are manufactured separately. E.G. printer well #1 contains thousands or millions of copies of chiplet-type #1, well #2 contains only 10^3s to 10^6s copies of chiplet-type #2, etc. So these "ink supplies" can all be manufactured separately, so a memory chiplet could be made on a wafer with process physics fine-tuned for RAM production, whereas a logic or multiplexing or signal-crossover chiplet could be made on a wafer using process physics tuned for logic LSI / VLSI production. Thus the individual ink types are manufactured in an optimal manner for the type of chiplet.
.
It's when the chiplets are "sprayed" or distributed onto the final substrate that the lasers are used to reposition and realign and reorient the chiplets in order to combine them into a composite computational structure. Or that's my reading of TFA (un /. like of me to RTFA, but I did!)...

Re:quality (0)

Anonymous Coward | about a year ago | (#43408257)

Yo Dawg....ahh, never mind.

Re:quality (1)

Khyber (864651) | about a year ago | (#43408719)

"What next? Tiny chiplet sections assembled to create tiny chiplets, then the ultimate goal of assembling components one atom at a time?"

You mean similar to the already-existing multi-core technology used in GPUs?

Re:quality (1)

serbanp (139486) | about a year ago | (#43409615)

Ahem, do you know how the multi-core GPU/whatever is made? All of the blocks sit nicely on the same die (except some MCM/stacked fancy stuff).

The article talks about "printing" (i.e. placing) small dies onto a holding substrate, similar to present-day PCBs. This has obvious penalties regarding footprint, communication speed, manufacturability and cost of both "tiny chiplet" production (where large amounts of wafer area will be wasted on scribelines) and assembly/testing.

A weird solution in search of a problem.

It's still silicon (4, Informative)

viperidaenz (2515578) | about a year ago | (#43407937)

TFA goes on to say it goes against 50 years of thinking. Spreading out transistors rather than putting them closer together.
They're still placing traditionally produced silicon wafers on what is effectively a printed circuit board. The wafers are just smaller. The method of placing them is new.

I don't see how spreading out parts of a system that operate in the many GHz range is going to help performance. You'll run into problems of electrons not passing charge quick enough because of that pesky speed of light thing. At 3GHz, light only travels 100mm per cycle. Electricity won't go further than 95mm in copper. Half that if you look at the speeds in parts of the core of old P4 processors, upwards of 7GHz.

Re:It's still silicon (0)

Anonymous Coward | about a year ago | (#43408103)

Still useful for parallelizable problems, and maybe they can go 3D and build cooling pipes into the structure.

Re:It's still silicon (0)

Anonymous Coward | about a year ago | (#43408131)

You can get a complete 32-bit ARM Cortex M-3 processor in 0.03 mm2 of silicon these days, and run it on 7 W/MHz. That's plenty for embedded applications, especially parallelizable ones where, you can just throw dozens of those cores at the problem.

Moore's law has also led to some unintuitive manufacturing realities. One of them is that the silicon chips themselves are cheaper to produce than the plastic/metal/ceramic packages they are mounted inside.

Technologies for better connecting multiple chips (like this, or stacking and bias), are *extremely* exciting. They're how we get from laptops and smartphones to sci-fi stuff like having thousands of processors woven into our clothes.

Re:It's still silicon (0)

Anonymous Coward | about a year ago | (#43408173)

That's 0.03 square millimeters ant 7 micro-watts per mhz. Something was lost in the translation.

Wandering "ant" interjecting itself . . . (1)

girlinatrainingbra (2738457) | about a year ago | (#43408271)

and either an "n" or an "ant" crawled into the middle of your "at" in the correction of your "lost in translation" phrase... :>)
That's 0.03 square millimeters ant [sic] 7 micro-watts per mhz. Something was lost in the translation.

Re:Wandering "ant" interjecting itself . . . (0)

Anonymous Coward | about a year ago | (#43408283)

Actually, a "d" became a "t".

wandering ant algorithm ? random walk ? . (2)

girlinatrainingbra (2738457) | about a year ago | (#43408379)

I thought maybe they created a new technique use ants and pheremones to deliver micro-chiplets to the appropriate site. Perhaps the beginning of a new algorithm for constructing items with the chiplets using biological delivery mechanisms. If it's a military project, they might use "soldier ants"! [wikipedia.org]
http://en.wikipedia.org/wiki/Ant_robotics [wikipedia.org]

Re:wandering ant algorithm ? random walk ? . (1)

Neil Boekend (1854906) | about a year ago | (#43409859)

Nah, that's simply Hex [lspace.org] . Useful if he wants to be, but disturbingly sentient at times.

Re:It's still silicon (1)

viperidaenz (2515578) | about a year ago | (#43408421)

That's only the core. no MPU, two interrupts, no debug, no trace, no memory of any kind. The M3 doesn't support an FPU either.
The M3 doesn't do MAC or SIMD. It's a microcontroller, not a microprocessor. It doesn't do much per MHz compared to an R or A-series ARM Cortex.

The M4 has an optional FPU and some MAC and SIMD stuff. It's also 33% larger and chews 14% more power.

It's basically the bare minimum as a compromise for low overall power consumption. Great product to put in your smart-watch, no so great for your PC.
There's also no support for SMP in that 0.03mm2, so you'll need something to pull the problem apart to parallelize it then put it back together again.

Re:It's still silicon (1)

Khyber (864651) | about a year ago | (#43408731)

Putting this in a smartphone form factor would pretty much make everything you said a moot point.

Let's say the size of my ZTE Score 500.

Re:It's still silicon (1)

viperidaenz (2515578) | about a year ago | (#43409025)

Show me a smartphone with no MPU/MMU.

Re:It's still silicon (1)

Khyber (864651) | about a year ago | (#43412427)

My older phone is powered by a FA606TE 32-bit RISC CPU based on V5TE instruction set without MPU, MMU, and LBC, no cache controller, no scratchpad controller.

That was like 2009.

Re:It's still silicon (1)

viperidaenz (2515578) | about a year ago | (#43415679)

So which smart phone uses that 2007 era CPU?

Re:It's still silicon (1)

Khyber (864651) | about a year ago | (#43422619)

Anyone that uses an ultra-low power ARMv5 core.

Like my ZTE Blade u880.

But you keep on being ignorant about technology, sayeth someone that works in semiconductors.

Re:It's still silicon (0)

Anonymous Coward | about a year ago | (#43427453)

Anyone that uses an ultra-low power ARMv5 core.

Like my ZTE Blade u880.

But you keep on being ignorant about technology, sayeth someone that works in semiconductors.

"Khyber Kitsune", earlier in this discussion, responding to someone who said that Intel's current process is 22nm:

I'll bet on the traces being even smaller than that. You must mean transistor size.

FYI, there is a giant tell in your little "bet" that you don't actually work in semiconductors, especially not anything related to high performance logic.

Judging by your slashdot journal, you're involved in some kind of business assembling LED lighting. That does not mean you "work in semiconductors", dude. You work with them. And you're specialized in working with the simplest possible devices. One LED diode is literally one PN junction. You can't get simpler than that. Stop trying to claim expertise you don't have.

Re:It's still silicon (1)

Khyber (864651) | about a year ago | (#43430025)

Oh how naive you are.

But of course you chose to post AC and prove nothing.

And LED is just the more popular of my semiconductor work around the globe.

But you keep trying. 22nm means the half-pitch (aka half the distance) between identical memory cells, or transistors.

And we have traces smaller than that. They're used in joining diodes together in a single package.

Judging by your cowardice and lack of knowledge or information, you know nothing.

Seeya.

Re:It's still silicon (0)

Anonymous Coward | about a year ago | (#43543233)

Looked this up since I just responded to another of your electronics-related flames in a more current discussion, remembered this one, and wondered if you'd responded.

First, I post AC because I don't have a slashdot account. Why? Well, one reason is that it's perpetually amusing to see slashdot idiots flaming ACs for posting AC, as if that had anything to do with the truth of the words in the post.

Next, the tell I referred to is that in modern logic processes, traces are generally on a coarser pitch than the single number bandied about as describing that node. Not finer, as you claimed. A 22nm logic process will usually have a contact and wiring pitch much coarser than 22nm. Also note that metal pitch varies; usually, the higher you go in the layer stackup, the coarser it gets. And finally, it's worth noting that only the bottom-most metal layer (M0 or metal 0) is printed at the finest possible metal pitch.

Next, no, 22nm is not necessarily "half the distance between identical memory cells, or transistors". Yes, that's the answer you'll come up with if you google for phrases and scan the first few results. It's not the complete picture. The truth is that numbers like 22nm have a... complicated relationship with feature sizes. It's highly dependent on the exact kind of thing being made -- when a flash memory process is described as 20nm, that tends to mean something quite different from what's implied by a 22nm logic process. It's also manufacturer-dependent -- one manufacturer's 22nm logic process might have significantly different printed feature sizes than another 22nm logic process. And even fundamentally different structures being printed. Intel's 22nm logic uses FinFET transistors, which are quite different from conventional planar transistors, in ways which are very relevant to calculating area.

Basically it's a mess. Which you'd know if you actually worked in the field. Which, as you seem hellbent on proving, you don't. Like this howler, concerning 22nm wiring:

And we have traces smaller than that. They're used in joining diodes together in a single package.

Uh, no. You (or, to be more precise, the suppliers who send you LEDs, since you don't actually work for a LED device manufacturer) cannot use 22nm traces to join LED diodes together in a single package. Do you have any fucking idea how little current it takes to vaporize a wire with a 22nm cross section? Do the math!

(Note: one of the reasons why logic chips have variable-pitch wiring is that the fine-pitch bottom layers can't even be used for power distribution. Not enough cross section in the conductors.)

I do hope you keep on attacking people who post AC for being "cowards" while posting with an anonymous, made-up name. It's funny enough when people who post with what look like real names do that, but it's priceless when asshats like you do it.

Re:It's still silicon (1)

viperidaenz (2515578) | about a year ago | (#43428021)

That phone has an MMU. It runs Android which requires one. It's built on Linux, not UCLinux.

Who's the ignorant one now?

Re:It's still silicon (1)

Khyber (864651) | about a year ago | (#43430035)

>doesn't know about libraROMs which has custom Droid w/o MMU
>doesn't know shit about the hacked ROM community

Typical 7 digit.

Re:It's still silicon (1)

viperidaenz (2515578) | about a year ago | (#43434953)

care to share an actual link?

Re:It's still silicon (0)

Anonymous Coward | about a year ago | (#43411763)

Could be useful for Neuron Emulation. Can get an emulator that can emulate a mouse down from the size of an office building to the size of a 42u server rack.

Re:It's still silicon (0)

Anonymous Coward | about a year ago | (#43408953)

That's 0.03 square millimeters ent [wikipedia.org] 7 micro-watts per mhz. Something was lost in the translation.

FTFY

Re:It's still silicon (0)

Anonymous Coward | about a year ago | (#43410095)

Slashdot still hasn't fixed the character set encoding on their MySQL database that was first reported to them over a decade ago.

Hint to slashdot: "DEFAULT CHARSET=utf8 COLLATE=utf8_unicode_ci"

Re:It's still silicon (0)

Anonymous Coward | about a year ago | (#43408255)

Technologies for better connecting multiple chips (like this, or stacking and bias), are *extremely* exciting. They're how we get from laptops and smartphones to sci-fi stuff like having thousands of processors woven into our clothes.

Back in my day we carried our processors in our pockets... .. in the snow .. .. uphill both ways ... .. and we liked it!

Re:It's still silicon (0)

Anonymous Coward | about a year ago | (#43408327)

And "stacking and bias" should be "stacking and vias". I blame autocorrect for that one.

Oh, and the captcha for this post is "stammers"...

Re:It's still silicon (1)

viperidaenz (2515578) | about a year ago | (#43408331)

Chip-on-board is a method used to remove the plastic/metal/ceramic packages. It's been around for decades. If you look inside something cheap from China and there is a blob of black stuff in the middle of the PCB, its epoxy protecting the wafer that has been bonded directly to the PCB.

Re:It's still silicon (1)

DerekLyons (302214) | about a year ago | (#43408209)

I don't see how spreading out parts of a system that operate in the many GHz range is going to help performance. At 3GHz, light only travels 100mm per cycle.

Presuming of course that the system operates in the many GHz range, or even needs to. Not to mention that you can pack a *bunch* of chiplets (each the size of a grain of sand and holding thousands of gates) in an area 100mm on a side.

Re:It's still silicon (2)

dissy (172727) | about a year ago | (#43408697)

I don't see how spreading out parts of a system that operate in the many GHz range is going to help performance.

But that is why they are doing this, to not spread them out like we are right now, to avoid the performance problems we have right now.

In your computer, your CPU is in one package, the RAM in another, the GPU in another. They all attach to extremely long wires on a device known as a mother board.

Instead of having one wafer with 1000 CPUs on it, broken apart and packaged in huge plastic boxes to be connected to other components over very long wires like we currently do, they will have one wafer with 1000 different chips on it each a component of a computer.

Instead of the CPU being hundreds of mm away from the RAM, they plan on putting them within 1mm of each other on the same wafer.

Your entire computer will consist of a wafer being able to fit in a plastic package smaller than your current CPU, except it will be everything on your motherboard and that is plugged into that motherboard, all in one chip.

If our mess of huge wires on motherboards lets us reach 10ghz with liquid cooling right now, imagine when the circuits are thousands of times shorter using this new method.

Re:It's still silicon (1)

viperidaenz (2515578) | about a year ago | (#43409065)

In my computer, virtually all the of high speed logic is in the CPU, bar the DRAM.
The CPU, cache, GPU, memory controller, all on the same package. Like all desktop Intel CPU's.

Intel/Micron already have a technology called "hybrid memory cube" that stacks silicon on top of each other in the same chip, so you can put ram on top of the cpu.

NVidia are going to use it under the marketing term of "Stacked DRAM".

A step behind this is "package on package" used in smartphones and the raspberrypi. The RAM chip is soldered on top of the SoC chip.

Re:It's still silicon (0)

Anonymous Coward | about a year ago | (#43408879)

How about a wall sized display with one microprocessor/pixel?

Re:It's still silicon (0)

Anonymous Coward | about a year ago | (#43410601)

um, frequency has nothing to do with propagation delay in a transmission line

..and your brain runs at a couple hundred Hz (1)

xtal (49134) | about a year ago | (#43412807)

It's all in the architecture. It looks like these systems could be effectively used to marry custom silicon to very high frequency cores produced using traditional techniques.

Amazing stuff if it goes to production.

rrefefaf (0)

Anonymous Coward | about a year ago | (#43408059)

WOW! They invented the flip-chip package! NOT!
Fucking retards will say anything to pump up their worthless stock

"dies"? Isn't it "dice"? (0)

Anonymous Coward | about a year ago | (#43408061)

Why "dies" and not "dice"?

I'm likely to be flamed by the grammarians. I guess I'll just roll the dies on that.

Re:"dies"? Isn't it "dice"? (2)

viperidaenz (2515578) | about a year ago | (#43408311)

Because they're not talking about rolling a dice. The plural for "die", as in a stamp or a mold is "dies"

Re:"dies"? Isn't it "dice"? (0)

Shavano (2541114) | about a year ago | (#43408339)

Dice is correct. "Dies" is the past tense of a verb.

Re:"dies"? Isn't it "dice"? (1)

Khyber (864651) | about a year ago | (#43408735)

This coming from someone that has never worked with tool and tap dies before, obviously.

Re:"dies"? Isn't it "dice"? (0)

SoulNibbler (2194576) | about a year ago | (#43410367)

except for they aren't refering dies as in what you use to smash semi-soft metal into new shapes but actually dice, as in what you get after you dice (or cut up) a wafer.

TLDR: you are correct with tool dies, he/she is correct with wafer dice.

Re:"dies"? Isn't it "dice"? (1)

K. S. Kyosuke (729550) | about a year ago | (#43411617)

OED says that "a cubical block" in architecture, when called "die", has also the regular plural of "dies". It seems that the users of this word in the IC context take a lot of liberties with it.

Re:"dies"? Isn't it "dice"? (0)

Anonymous Coward | about a year ago | (#43411805)

TLDR: you are correct with tool dies, he/she is correct with wafer dice.

So you're saying that a die makes a die, but dies make dice?

Re:"dies"? Isn't it "dice"? (1)

Shavano (2541114) | about a year ago | (#43411123)

Sure I have. I just had forgotten about them for the moment. But the little square things you get when you chop something in little square pieces? Those are called dice.

Re:"dies"? Isn't it "dice"? (0)

Anonymous Coward | about a year ago | (#43419113)

because we did an empirical study of english, we even included american english.
we found one -- exactly one moron, who got it wrong.
even the japanese got this one right.
statistically speaking, it will take until the heat death of the universe before another dope like you comes along.

herppggaoggpherp (0)

Anonymous Coward | about a year ago | (#43408097)

WOW! They invented the flip-chip package! NOT!
Fucking retards will say anything to pump up their worthless stock

Ooooohhh - wafer scale integration (1)

NoNonAlphaCharsHere (2201864) | about a year ago | (#43408127)

Wasn't Gene Amdahl trying to do this back in the late 70's? Yeah, thought so.

Re:Ooooohhh - wafer scale integration (2)

Areyoukiddingme (1289470) | about a year ago | (#43408313)

Well no. It's just multi-module packaging using a slightly odd chip placement technique. Getting a chip into a package that can safely be handled by a pick and place robot is a significant part of the expense in constructing chips. Packageless pick and place would seem like a valuable idea, and presumably fluids and magnetic fields can be more delicate than any mechanical robot. Pick and place all your chips "naked", then slap a lid on the result, and you can cram an entire motherboard worth of components into much less space than usual. It's a PC in a chip, without losing modularity and wafer yields.

That guy trying to build an entire PC into the PCMCIA form factor has the same idea, though he still has to use discrete chips and a board inside his package, so it's thicker than it otherwise might be, and considerably far away from the state of the art in performance. This is the natural evolution of that idea, so to speak, and presumably it could meet or exceed the state of the art in performance. Heat dissipation strikes me as being a serious problem though.

Re:Ooooohhh - wafer scale integration (1)

Neil Boekend (1854906) | about a year ago | (#43410055)

They may even be able to build useful capacitors in the package. That is difficult with current lithographic processes, but if one could use more low precision layers one may be able to build a capacitor with more than a couple of pF of capacitance (and not too many of those pesky pH's). Slapping a couple of dozen low precision layers on a normal wafer would be difficult and expensive. Using this tech to assemble a chip after litho could mean useful in chip capacitors.
In chip resistors could be improved too.
These things may seem relatively useless (chip manufacturers spend a lot of time preventing capacitance) but a well placed capacitor or resistor can do wonders for your EMC performance.

Here's the patent application (4, Informative)

Required Snark (1702878) | about a year ago | (#43408193)

http://www.google.com/patents?hl=en&lr=&vid=USPAT7332361&id=l--nAAAAEBAJ&oi=fnd&dq=Xerographic+micro-assembly&printsec=abstract#v=onepage&q=Xerographic%20micro-assembly&f=false [google.com]

It has the same components as a traditional Xerox machine. There is a drum that rotates and their positioning technology put the chiplets in precise locations on the substrate. The chiplets are in a fluid that acts like toner.

It appears that the performance depends on how fast the substrate conducts signals. At this point it seems unlikely that this is as fast as an on chip connection, but there seems to be no intrinsic reason that it would be any slower then the wires that hook a chip pad to a package pin. In aggregate the speed might be faster then a circuit board because the chiplits could be closer together then chips on a board.

One possible deployment would be to use this to assemble components which are then packaged in a standard IC. It's like an SOIC, except the parts are not all on one piece of silicon.

There are potential economies of scale. With an inventory of chiplets, and automation to make the interconnect substrate with CAD, a custom assembly line can create vast numbers of different configurations and not have to include a foundry in the loop.

Despite all the naysayers that have already posted, this is a potentially game changing technology.

Re:Here's the patent application (1)

Shavano (2541114) | about a year ago | (#43408363)

I'm having trouble seeing this as a viable manufacturing technique. How do you make the chiplets go down on the substrate in the desired orientation?

Re:Here's the patent application (2)

Khyber (864651) | about a year ago | (#43408741)

Same way reflow-soldering does it - surface tension, plus the possibility of two-way transistors and ICs.

Re:Here's the patent application (1)

Required Snark (1702878) | about a year ago | (#43408783)

That's why I posted a link to the patent application. In theory, if you post on Slashdot you should be smart enough to follow the link and be able to figure this out yourself.

Here's an overview from the patent:

The systems and methods described herein include in an example embodiment an electromechanical micro-assembler, described below, to fabricate a micro-assembly from a set of one or more micro-objects. An example fabrication process includes the following basic steps:1) encoding each micro-object with a charge that identifies the micro-object and specifies its orientation; 2) transporting the micro-objects from a sorting unit (that acts as a reservoir) to an imaging device using a dynamic electrostatic field; 3) writing an electrostatic image onto a substrate using an xerographic imaging unit; 4) delivering and interfacing the micro-objects to the substrate; and 5) performing post-processing of the micro-objects and the substrate form the final micro-assembly.

They put a structured electrostatic charge on each chiplet using xerographic technology. They put opposite matching charge on the substrate, also using xerography. The mechanism coveys the chiplet to the target position on the substrate, where electrostatic forces move the chiplet to it's final position. They then fix the chiplet to the substrate.

I know that not everyone who looks at stuff here is an uber-geek, but at least try and find things out for yourself. You'll learn more in the long run.

Re:Here's the patent application (1)

AcesDnied (2542270) | about a year ago | (#43408851)

Referencing an earlier comment "laser placement" to paraphrase. Not that I know how reliable that would be, however, I have seen some interesting articles dealing with the orienting of objects with lasers.

BTW most interesting conversation I've seen at /. in a while here.

Re:Here's the patent application (1)

AcesDnied (2542270) | about a year ago | (#43408857)

Ignore all that crap. Didn't bother to read as Snark suggested.

Re:Here's the patent application (1)

TubeSteak (669689) | about a year ago | (#43409145)

Despite all the naysayers that have already posted, this is a potentially game changing technology.

A game changer for whom?
If it isn't fast, then it's going to be relegated to embedded applications.
That may be a game changer for the embedded field, but your average consumer knows fuck all about embedded chips.

Re:Here's the patent application (1)

SoulNibbler (2194576) | about a year ago | (#43411183)

So why is this a game changer?
Well its not yet but it could be...
So basically we have to make small chips, this is because the parasitics decrease with size so we get more efficient as we get smaller (up to a point), we also get cheaper for simply geometric reasons (wafer/exposure area pretty much fixed cost) so yay more goodies from a chip.

Except...
Tooling up is expensive and HARD, dude what do you mean a .032m lithography mask costs $500,000+ and it probably won't work perfectly for at least a couple of revisions??! That sucks!

Why is this placement technique cool?
One of the neat uses for big chips today are graphics chips. They are huge but relatively simple, they have a bunch of repeated processing units and a buttload of cache and some neat front end or back end. The top generation GPUs are usually made about as big as one can physically make a chip (we normally expose wafers in chunks, and precision and field of view are competitive design goals when thinking about the optics for these systems), because they problem is embarrassingly parallel we can use all that performance and it even scales reasonably well across multiple cards/nodes. So imagine we could make a functional dice that contains a very small number of processing units, some cache and some glue logic that makes it easy to connect to some magical buss, now we can make a GPU as big as we want. If we are a GPU company we like this since we now have something like linear scaling for processing costs to go to MUCH bigger chips, which means we can sell a new super computer every few years without having to compromise our consumer line.

Other cool things:
Lab on a Chip, you can throw down MEMS and processing components on a small device, imagine a full digital assay built into the pricking needle.
Harry Potter Newspapers, if you can do alignment and finishing after the fact you can print your e-ink display and driver in whatever size you need. All thats needed is good yield on the sub-displays.
Disposable-lazy-electronics, we are getting here anyway with RFID, but how cool would it be to carry a roll of stickers that would act as line of sight GPS extenders but were solar or wifi powered. Add some sensors and you have a crowd-sourcable metro monitor that knows where every train is and what stops are crowded.

To summarize, this invention has to capability to possibly decrease the cost of sticking widgets together, thus we can have many little widgets instead of monolithic widgets.

DEEP THOUGHTS BY JACK HANDY !! (0)

Anonymous Coward | about a year ago | (#43408197)

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PARC researchers will spend the next 50 years (0)

Anonymous Coward | about a year ago | (#43408225)

Rediscovering manufacturing techniques.

embed it (0)

Anonymous Coward | about a year ago | (#43408373)

It would be better if they embed this in an epoxy or something that is electrical non-conductive, but carries heat.

A new life (1)

Anonymous Coward | about a year ago | (#43408725)

And before our eyes, a new life form is born. 3D printers = "birth machines". As a mental exercise, factor in a number of years worth of Moore's law-driven enhancement of 3-D printer capabilities. Brave New World indeed...

Re:A new life (0)

Anonymous Coward | about a year ago | (#43408931)

Your prose and writing are top notch, but your grasp of reality is not.

Not everything that ends with "indeed" is insightful.

I nearly puked when I read this. (0)

Anonymous Coward | about a year ago | (#43408891)

"system that makes smart objects with computing woven right into them."

Too rich in buzzwords for me to handle.

defect problem must be overcome (0)

Anonymous Coward | about a year ago | (#43409319)

the reason they make hundreds seperate them and recombine them is because the 'yield' (good ones without defect) need to be kept and defectives discarded. The more complex the item the lower the yield. They allievaiate this on some complex chips by having redundant circuitry that allows a defective section to be disabled and the remaining sections still used.

So how is this new 'printing' process to get past this problem especially as they are proposing to combine everything at once to one huge extra complex whole unit ???

They probably have to do that redundancy scheme (expending space) and maybe if they are clever an 'on-the-fly' adjustment of this 'printing' (requiring validation testing all along the way) as they progressively build the one big circuit.

perhaps for less complex but more varied circuitry the basic yield will pay off (or it would be higher cost items that can afford to throw away 4 to get one good one

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