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Sun Unveils Direct chip-to-chip Interconnect

Hemos posted more than 10 years ago | from the faster-then-a-speeding-bus dept.

Sun Microsystems 185

mfago writes "On Tuesday September 23, Sun researchers R. Drost, R. Hopkins and I. Sutherland will present the paper "Proximity Communication" at the CICC conference in San Jose. According to an article published in the NYTimes, this breakthrough may eventually allow chips arranged in a checkerboard pattern to communicate directly with each other at over a Terabit per second using arrays of capacitively coupled transmitters and recievers located on the chip edges. Perhaps the beginning of a solution to the lag between memory and interconnect speed versus cpu frequency?"

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First Post advocating the genocide of Arabs! (-1, Flamebait)

Anonymous Coward | more than 10 years ago | (#7023928)

There will never be peace in the Middle East until they are all dead.

Re:First Post advocating the genocide of Arabs! (-1, Redundant)

lanswitch (705539) | more than 10 years ago | (#7023965)

Does "terrabit" mean that it will be made of pieces of the earth?

Terrabit (-1, Offtopic)

Anonymous Coward | more than 10 years ago | (#7023934)

Insert obligatory stupid Bush Remark here.

- DRFSR

look, the point of all this is (-1, Offtopic)

Anonymous Coward | more than 10 years ago | (#7023944)

my butt smells

that's because... (0)

Anonymous Coward | more than 10 years ago | (#7024335)

It will be running java (5, Funny)

holzp (87423) | more than 10 years ago | (#7023947)

therefore the speeed increase will be unnoticable.

check this shizle my nizle (-1)

Anonymous Coward | more than 10 years ago | (#7024190)

Your Mom is so fat, if she was a c variable, her initialization would look like this: yourMom = (TFAT*) malloc(sizeof(YOUR_MOM)); //Stack Overflow

Re:check this shizle my nizle (-1)

waitigetit (691345) | more than 10 years ago | (#7024274)

You misspelled shizzle, nizzle and yo, whizzle.

Actually, you mispelled them.... (0)

Anonymous Coward | more than 10 years ago | (#7024299)

and here's my proof [books-rose.com]

Re:Actually, you mispelled them.... (0)

lanswitch (705539) | more than 10 years ago | (#7024349)

so please pell them again?

Re:Actually, you mispelled them.... (0)

Anonymous Coward | more than 10 years ago | (#7024533)

die.

Re:check this shizle my nizle (0)

Anonymous Coward | more than 10 years ago | (#7024636)

malloc allocates off the heap, not the stack, MORON!

You Java programmers are one step above VB programmers!

Timing? (3, Interesting)

afidel (530433) | more than 10 years ago | (#7023949)

I wonder if this release might have been pressed forward a bit to squelch some of the talk about Sun losing their will to innovate after Bill Joy left.

Re:Timing? (5, Insightful)

Usagi_yo (648836) | more than 10 years ago | (#7024011)

No. What you don't understand or realize is that Bill Joy actually left 2 years ago, when he "retired" into distinguished senior engineer, from CTO. This latest move by Bill Joy, full retirement is merely a continuation of that. At least thats how I see it.

Slashdotted (-1)

cerskine (202611) | more than 10 years ago | (#7023951)

Slashdotted - posting in Italian to avoid accusations of karma-whoring:

Il martedi il 23 settembre, i ricercatori R. Drost, R. Hopkins ed I. Sutherland del sole presentera "la comunicazione di prossimita" di carta al congresso di CICC in San Jose. Secondo un articolo pubblicato nel NYTimes, questa innovazione puo finalmente permettere i circuiti integrati organizzati in un modello della scacchiera per comunicare direttamente con a vicenda sopra ad un Terrabit al secondo usando gli allineamenti dei trasmettitori capacitively coppia e dei recievers situati sui bordi del circuito integrato. Forse l'inizio di una soluzione al ritardo fra la memoria e l'interconnessione accelera contro frequenza del CPU?"

Re:Slashdotted (-1, Offtopic)

Anonymous Coward | more than 10 years ago | (#7023991)

Whore di karma!

Hmm (1)

Mysticalfruit (533341) | more than 10 years ago | (#7023961)

This sounds like a sweet technology. Hopefully we'll see this in a real product in the near future.

Though the way people talk about SUN, were more likely to see it licensed to some other company...

Re:Hmm (-1, Troll)

eudaemon (320983) | more than 10 years ago | (#7024017)

Au contraire --

This is exactly the technology push they need to squelch all the
"SUN's CPUs stink" crowd.
(Assuming they can make it work, of course.)

I'll bet dollars to doughnuts it never runs Linux, either.

You'll only see two people with this tech: SUN and IBM.

SUN because they invented it and IBM because they'll patent every variation they can think
of on this idea by next Tuesday,
thus forcing SUN into a cross-licensing deal.

Re:Hmm (1, Insightful)

Daniel Dvorkin (106857) | more than 10 years ago | (#7024145)

If IBM has it, it will run Linux.

Chip to Chip technology? (1)

TWX (665546) | more than 10 years ago | (#7024288)

Isn't that called a trace? Or another fancy name would be a lead? I think that there are people with prior art...

Innovation is cool (-1, Offtopic)

192939495969798999 (58312) | more than 10 years ago | (#7023977)

I must say, I am super-glad to see that this has come out publicly now. Rock on, Sun! By the way, I am wrapping up my Sun internship, and they want me at the HQ or not at all! DOH! Still, best of luck with the new technology... I want one on my desktop!

Zhava? Sun Sucks! (-1, Troll)

Anonymous Coward | more than 10 years ago | (#7023980)

SUN CR1PPLED GN0ME!
SUN PI1SED ON THE L1NUX COMMUN1TY!
SUN == M1CROSOFT OF UN1X!
M0D D0WN 1F Y0U AGREE, M0D UP IF Y0U DISAGREE.

Mod parent up! (-1, Offtopic)

Anonymous Coward | more than 10 years ago | (#7024671)

I'd give you mod points, but I have a policy of metamodding all negative moderation as "unfair", and hence have none. Mod points, that is.

terrabit (2, Funny)

lanswitch (705539) | more than 10 years ago | (#7023985)

Does "terrabit" mean that it will be made of pieces of the earth?

Re:terrabit (0)

Anonymous Coward | more than 10 years ago | (#7024132)

You mean those silicon chips with ceramic packaging? They sure will!

Re:terrabit (0)

lanswitch (705539) | more than 10 years ago | (#7024181)

And they call that news? Most of the stuff around me is made of bits of the earth. Some bits are more processed than others, but they are still b.o.t.e.

ob: Carl Sagan was a hypocritical pothead quote! (0)

Anonymous Coward | more than 10 years ago | (#7024695)

You are WRONG.

They're actually made of bits of exploded stars.

No registration (5, Informative)

Anonymous Coward | more than 10 years ago | (#7023987)

Via Google [nytimes.com]

Terrabit Terrabit Terrabit (-1, Troll)

Anonymous Coward | more than 10 years ago | (#7024003)

Ooops, a typo :)

Terrabit Terrabit Terrabit
Terrabit Terrabit Terrabit
Terrabit Terrabit Terrabit

(Stupid fag filters)

Replacing Network-on-Chip/System-on-Chip (4, Interesting)

KarmaPolice (212543) | more than 10 years ago | (#7024012)

This could prove very interesting as the speed usually drops when "leaving the chip" to do communications. There has been alot of research to develop protocols to ease on-chip communication when several ICs are combined on a single chip. If Suns technology can stand the test, NoC/SoC products could reduce it's time-to-marked dramatically...smaller and faster devices for everyone!

BTW: I didn't RTFA since it requires (free) reg.

OT: Why register for /. but not NYT? (0, Offtopic)

Mignon (34109) | more than 10 years ago | (#7024587)

BTW: I didn't RTFA since it requires (free) reg.

You feel strongly enough about registering at the NYT to mention it in your interesting post, but you registered for Slashdot where registration isn't required for reading articles or even posting. Just curious - what's the difference?

Respectfully,
"Mignon"

Re:OT: Why register for /. but not NYT? (-1, Offtopic)

Anonymous Coward | more than 10 years ago | (#7024684)

After registering for slashdot, you get to attach your name to things you say....

I suppose this will be patented... (3, Funny)

Thinkit3 (671998) | more than 10 years ago | (#7024014)

Or maybe Rambus is already fixing to sue them.

Re:I suppose this will be patented... (0)

Anonymous Coward | more than 10 years ago | (#7024041)

Ramb...who? Havn't they died in a flaming ball of shit yet?

I havn't seen a RIMM in over a year now. Do Intel even make Rambus Northbridges (Sorry, Memory Interconect Hubs) anymore?

Fast today Slow Tomorrow (5, Interesting)

Anonymous Coward | more than 10 years ago | (#7024022)

That is the nature of the beast.

Remember how excited you were to get your hands
on a 386 machine?

The thrill of your first encounter with a 286 screamer?

Upgrading to 16k from 4k on your TRS-80?

Your first disk drive for your Apple 2?

It's all relative.

So enjoy

SUV of chip interconnects? (3, Funny)

Atomizer (25193) | more than 10 years ago | (#7024030)

Whatever, I think this will end up being the SUV of chip to chip conections. ;)

Re:SUV of chip interconnects? (0)

ikkonoishi (674762) | more than 10 years ago | (#7024078)

More likely it will be the model T of chip to chip connections since it is a prototype.

Re:SUV of chip interconnects? (1)

stratjakt (596332) | more than 10 years ago | (#7024157)

The Model T was a production car.

Re:SUV of chip interconnects? (1)

Slightly Askew (638918) | more than 10 years ago | (#7024246)

And the Obscure Analogy Award goes to...

OT: Re:SUV of chip interconnects? (1)

Slightly Askew (638918) | more than 10 years ago | (#7024270)

Arrgh! That's twice. I'm gonna have to start reading at the bottom of the page so I can catch the references to other articles.

Pictures of the technology. (-1, Troll)

Anonymous Coward | more than 10 years ago | (#7024038)

This techology has been discussed for decades, but it has only been economicly feasable for a few years now. Here are some diagrams of how it works [books-rose.com]

http://www.books-rose.com/v_12/

Must Not... (-1)

ikkonoishi (674762) | more than 10 years ago | (#7024039)

Must... resist... Beowulf... cluster... joke....

This is really cool.

The main problem I see is how much heat all these things will generate right next to each other.

Also it might become hard to get at the chips if they are right next to each other.

Link via Google (no Reg. Required) (4, Informative)

chrestomanci (558400) | more than 10 years ago | (#7024058)

Re:Link via Google (no Reg. Required) (1)

ConceptJunkie (24823) | more than 10 years ago | (#7024401)

That's nothing... thermal expansion and vibration have been unseating my circuit boards for years.

IANAEE (I am not an electrical engineer) (4, Insightful)

Peridriga (308995) | more than 10 years ago | (#7024084)

This might be the obvious question but, why hasn't anyone done this before?

It seems obvious, the end of chip has pins. The chip it will eventually connect to has pins. Instead of having 20 trace lines to the next chip why not redesign them so the out/inputs of both line up to reduce the complexity of the design.

Anyone wanna fill in my mental gap for me?

Re:IANAEE (I am not an electrical engineer) (0)

Anonymous Coward | more than 10 years ago | (#7024133)

The main bottleneck in CPU performance is memory access. It doesn't matter if you have a grid of super processors if getting data from memory takes a trillion cycles. So i guess it hasn't been done before because it wouldn't help much. And yes, that memory wall is still an issue.

Re:IANAEE (I am not an electrical engineer) (1, Insightful)

ikkonoishi (674762) | more than 10 years ago | (#7024174)

The main bottle neck is memory access because of the system bus.

A direct CPU to RAM connection would improve things dramatically.

Why do you think L1 cache is so important?

Re:IANAEE (I am not an electrical engineer) (2, Informative)

fitten (521191) | more than 10 years ago | (#7024337)

So you think DRAM access time is 40ns (or so) because of the system bus?

L1 cache typically found on today's processors and DRAM are two different things with different design targets. Pick up a VLSI book.

Re:IANAEE (I am not an electrical engineer) (5, Informative)

eXtro (258933) | more than 10 years ago | (#7024590)

There are two seperate metrics that define the speed of memory. Latency, which is what your 40 ns refers to, and bandwidth. Large caches address the latency problem as you stated. If you want to transfer more bits per cycle you're restricted due to signal integrity issues related to the bus, so the parent post is also correct. You can increase the width of the bus, up to a point, and get a small scalar increase in bandwidth. To go beyond this you need to address signal integrity problems.


Sending fast edges over a bus is difficult because the signal degrades:

  • inter-signal interference: Each parsel of information spreads due to the RC nature of the bus so that it takes up more than a period, thus interfering with the next packet.
  • cross-talk: Each wire on the bus is fairly tightly coupled with it's neighbours, so switching activity on one wire affects it's neighbours.
  • transmission line effects: Package connectors, bends in circuit traces etc all create impedance mismatches. This causes reflections which degrade the signal.


If your dataset fits into the cache well, which is often the case for PCs, then a cache can fix most of your problems. If you're dealing with datasets that span gigabytes or terabytes and your application can't be subdivided such that processing and memory can be constrained per cpu then your cache doesn't assist you very much.

Re:IANAEE (I am not an electrical engineer) (5, Insightful)

Jah-Wren Ryel (80510) | more than 10 years ago | (#7024187)

It has been done before, probably the most recent incarnation is hypertransport from AMD. The only difference at the 50,000ft view is that the speeds and feeds are faster. This is an evolutionary step, not revolutionary or innovationary,

Re:IANAEE (I am not an electrical engineer) (1, Informative)

proj_2501 (78149) | more than 10 years ago | (#7024257)

HyperTransport is more than AMD. In fact, it includes Sun!

from the HyperTransport FAQ [hypertransport.org]
"6. What is the current specification release?
The current HyperTransport Technology Specification is Release 1.05. It is backward compatible to previous releases (1.01, 1.03, and 1.04) and adds 64-bit addressing, defines the HyperTransport switch function, increases the number of outstanding concurrent transactions, and enhances support for PCI-X 2.0 internetworking."

ibm storage bricks... (1)

simpl3x (238301) | more than 10 years ago | (#7024417)

ibm has layed out similar plans for modular storage blocks (http://www.google.com/search?sourceid=navclient&i e=UTF-8&oe=UTF-8&q=ibm+storage+bricks) connected by pads on the surfaces. good luck patenting that, unless the application was made a couple of years ago.

Re:IANAEE (I am not an electrical engineer) (0, Flamebait)

proj_2501 (78149) | more than 10 years ago | (#7024189)

Yeah, YOU try to coordinate redesigns for 4 different chip vendors, who are also redesigning their chips for EACH OF THEIR CUSTOMERS.

Re:IANAEE (I am not an electrical engineer) (2, Informative)

jhines (82154) | more than 10 years ago | (#7024192)

It has been done.

The DEC PDP11/03 aka LSI-11 was implemented as a multi chip (4 + 1 rom) CPU. The 5 chips were placed right next to each other.

This chip set was also setup by others with the UCSD Pascal "p-code" as the instruction set.

Other CPU in the series had MMU, and additional instructions in additional chips.

Yes, sounds like the Transputer reinvented (1)

Angostura (703910) | more than 10 years ago | (#7024203)

Ah, the Inmos Transputer, ideal for parallel applications. Now as dead as a doornail.

Transputer background [classiccmp.org]

Re:IANAEE (I am not an electrical engineer) (2, Interesting)

Usagi_yo (648836) | more than 10 years ago | (#7024248)

Alot of reasons. We'll start with large complex chips. No, the pins aren't at the end of the chip, they are underneath the chip. BGA, CGA, LGA, ball grid, colume grid or land grid array.

Then we'll go to ... well, they sorta did. They just enclosed it into one big chip.

Then of course Heat and cooling and power requirments.

Then onto manufacturability and repairability. Don't want to have a $15k board that has to be thrown away whenever there are problems with it. You do want to be able to repair it.

Next on to glue logic or glue componants such as current limiting resisters, pull ups, pull downs, bypass and decoupling capacitance.

Re:IANAEE (I am not an electrical engineer) (1)

Loconut1389 (455297) | more than 10 years ago | (#7024293)

I think sun is talking about having -no- trace lines, the chips have transmitters and receivers rather than traces between chips.

Re:IANAEE (I am not an electrical engineer) (5, Informative)

Anonymous Coward | more than 10 years ago | (#7024321)

You can't simply just remove the circuit board to achieve better speeds, you need to eliminate the need for the pad that converts internal logic to what we currently use externally. That is what Sun is claiming they have done.

Sun's technology is not simply soldering to pins directly together (as you suggest), which is effectively the same thing as wiring through a circuit board. The high speed, low drive strength, low-voltage drivers have to go through pads that convert the internal signal to a slower, high drive strength, high voltage driver, that will yield a reliable connection to the next chip. I'm not an expert in this area, but Physics just gets in the way. There are capacitive issues, and interconnect delay issues.

Sun is claiming to use capacitive coupling (put the pins really close together, but don't physically connect them.) This way they don't have to drive the external load of the pin/board connection, and are claiming they will be able to scale this down to a pad that will be able to switch faster than existing physical wire connected pins. Which means they believe they can make this technology work with lower drive stengths.

They still have a ways to go. Notice that the P4 has faster connections using existing techology. Sun did a proof of concept, and claim they can speed it up 100x. So they haven't _proved_ that this will operate faster yet. They still have many things to overcome to make this viable, including how to make a mass production/assembly process. It's going to be a few years. At least.

Beginning of the end for SCO stock? (-1, Offtopic)

Anonymous Coward | more than 10 years ago | (#7024147)

I hope I hope I hope... I know this will be modded offtopic but you'll see it anyway. SCO's stock dived $2 in the first minutes of trading today. Could it be the start of a fiery spiralling end? hope so!

Re:Beginning of the end for SCO stock? (-1, Offtopic)

Anonymous Coward | more than 10 years ago | (#7024254)

Good work dude. You haven't seen stock markets much have you? It's back up again.

Imagine a Beowulf Cluster... (2, Funny)

tekiegreg (674773) | more than 10 years ago | (#7024151)

of these, well that's kind of the point actually :-)

Perhaps a physical base for Neural Network? (3, Interesting)

BlankStare (709795) | more than 10 years ago | (#7024163)

I wonder if this hardware computing model could provide the first real base for Neural Network computing? As far as I know, any neural network is currently emulated on linear processing machines.

Re:Perhaps a physical base for Neural Network? (1)

kinnell (607819) | more than 10 years ago | (#7024644)

I wonder if this hardware computing model could provide the first real base for Neural Network computing?

This is not a hardware computing model, it's a new interconnect technology. So no.

As far as I know, any neural network is currently emulated on linear processing machines

The neural network group [ed.ac.uk] at Edinburgh University has been developing parallel neural network chips using analog technology for some time now. Because neural networks are very fault tolerant, the errors introduced by analog adders and multipliers is not important.

Re:Perhaps a physical base for Neural Network? (1)

gkramer (614370) | more than 10 years ago | (#7024672)

>As far as I know, any neural network is >currently emulated on linear processing >machines. Not entirely true. A lot of people simulate neural nets on computers because its cheaper and easier. But my lab, and a lot of other people implement them in hardware for speed and compactness. NN hardware implementations have been in the literature for a long time.

FINALLY! (5, Interesting)

JoeLinux (20366) | more than 10 years ago | (#7024168)

Someone gets it. As an Electrical Engineer-in-training, I was always frustrated with people who got these big bad processors and wondered why their improvement was minimal.

They never quite grasped that the biggest bottleneck is between the processor and memory.

My EE instructor always said that they could improve performance by doing one simple thing: make the interconnects on the motherboard between the motherboard and RAM rounded instead of cornered. You could then increase bus speed as you wouldn't have magnetic loss at the corners like you do now.

You fix that, and you can see a SUBSTANTIAL improvement in performance. The only thing that can be done beyond that is to get a Platypus drive (Solid state "Hard Drive" made from Quikdata made from DDR RAM). Then you reduce your access time to your hard drive from milliseconds to nano/microseconds.

Re:FINALLY! (0, Flamebait)

javatips (66293) | more than 10 years ago | (#7024226)

My EE instructor always said that they could improve performance by doing one simple thing: make the interconnects on the motherboard between the motherboard and RAM rounded instead of cornered. You could then increase bus speed as you wouldn't have magnetic loss at the corners like you do now.


I hope that you instructor applied for a patent for this... If he did, he will be rich soon just be licensing this incedible breakthrough in interconnecting chips.


The actual good consequence is that he will stop teaching soon. I hate crappy instructor who think they have great idea to make stuff better, but do nothing with it... Especially, easy to implement improvements. If what he said to you was not full of crap, you can be sure that someone would have implemented this!

Re:FINALLY! (1)

Ella the Cat (133841) | more than 10 years ago | (#7024484)

It must be horrible to live life so cynically and literally. His instructor was saying something to make him =think= about what happens. There's a post a few down from yours about using 45 degree bends. Go check out High Speed Signal Propagation (Advanced Black Magic) by Johnson and Graham ISBN 0-13-084408-X [signalintegrity.com] . You might learn something.

Re:FINALLY! (0, Offtopic)

javatips (66293) | more than 10 years ago | (#7024596)

It must be horrible to live life so cynically and literally.


It is actually quite pleasant to live a life like this. I really enjoy it... You made my day!

Re:FINALLY! (1)

afidel (530433) | more than 10 years ago | (#7024259)

Obviously an EE in training =)
Have you ever tried to route a complex multilayer PCB design? If you have then you will know that it would be basically impossible to guarentee all straight paths between the CPU and RAM, or any other component. Besides if you want fast ram you put it on or near the CPU die. Hence processors like the Xeon, Itanium, HP PA-8800, etc which derive most of their performance gains over their desktop competitors by having large L2 and huge L3 caches.

Re:FINALLY! (2, Informative)

Jeff DeMaagd (2015) | more than 10 years ago | (#7024304)

I think the fourty five degree corners is about as much of a compromise as one can get without being too expensive with routing.

Another problem is that the speed of memory itself isn't that great unless you want to spend a _lot_ of money, to the tune of $50-$100 per megabyte as we see in advanced processor caches, and the faster it is, the more very power inefficient it becomes, maybe to a sizeable fraction of a watt per megabyte.

Re:FINALLY! (2, Interesting)

hackstraw (262471) | more than 10 years ago | (#7024457)

Other people "get it". If you go to UVA, you might want to talk with Dr. McCalpin, and take a look at the stream memory benchmark [virginia.edu] .

Memory bandwidth is a bottleneck, not the biggest. It depends on the application. Sometimes an app is CPU bound, disk bound, network bound, or memory bound (or graphics card bound if 130FPS is too slow for your eyes). Also, chip-to-chip interconnects will not change the memory bandidth issue, because if the data does not fit on the chips or thier cache, then its going in memory.

Also, this is for scaling. Think beowulf. For those machines, the data must go from the cpu -> memory -> network interface -> switch -> network interface -> memory -> cpu. Yes, bandiwidth is an issue, but there is also latency, which would be very low with these kinds of chips.

A side note, I work with a guy that soldered chips together like this which had native parallel processing instructions about 20 years ago.

Re:FINALLY! (0)

Anonymous Coward | more than 10 years ago | (#7024623)

McCalpin is at IBM, was at SGI before that, STREAM is just hosted at UVA out of tradition.

Is this new? (3, Insightful)

4im (181450) | more than 10 years ago | (#7024171)

Sounds a lot like the ol' Transputer (was from INMOS), of course faster. One could also think of AMD's HyperTransport. So, again, except maybe for the speed, I don't see much innovation here.

If only people could remember that "terra" has something to do with earth, "tera" is the unit...

Re:Is this new? (1)

TwistedSquare (650445) | more than 10 years ago | (#7024219)

I wouldn't say it was innovation but its a step in the right direction. Its very close to the CSP model as dealt with before (http://www.wotug.org/), which should allow for efficient use of multiple processors.

Re:Is this new? (2, Insightful)

Ella the Cat (133841) | more than 10 years ago | (#7024611)

It doesn't sound like the Transputer to me. Sure, they resemble each other in that you can build a 2D array of chips from them by design, but you miss (or inadvertently downplay) that the innovation occurs in the fundamental electronic engineering issue of what happens in the bits of circuitry that drive the pins/pads - the transputer used asynchronous links and conventional pins and a nice but conventional memory interface, the Sun chip is doing something new, or if not new, seldom seen and highly promising. Ivor Sutherland knows his stuff.

or it might not (3, Insightful)

penguin7of9 (697383) | more than 10 years ago | (#7024172)

Placing large numbers of chips adjacent to one another has obvious problems with heat and power, in particular when running at those speeds. That, rather than interconnect technology, is probably the main reason we still package up chips in large packages.

This might be useful for placing a small number of chips close together, in particular chips that may require different manufacturing processes.

Re:or it might not (2, Insightful)

Derivin (635919) | more than 10 years ago | (#7024464)

Heat will definatly be an issue, but much less power will be required. The majority of the power required by chips is used to push data on and off the chip. It takes alot of poser to move a signal from a 25 micron PCB path.

This technology (if it pans out) will mostlikly enter teh private sector in cell phones, DVD players and other small consumer electronics that have a very large number of units produced.

Silicon wafer production has always had one major problem. Impurities. The ability to use more of the waffer to produce smaller chips that can later be 'put back together' in arrays that may not be any larger than the origional single chip solution has the potential to be much cheaper to manufacture in mass quantity.

Granted this is part of the theory behind 6 Sigma, which does not always work out.

Cooling with dielectric? (1)

SkiItIfYouCan (523527) | more than 10 years ago | (#7024697)

I bet they could bath the board in a dielectric liquid that would increase the capacative coupling, while also removing heat more efficiently. Not sure what this liquid would be, but those guys at Sun are smart, they can figure it out.

Burning Slashdotter Questions (0, Troll)

teamhasnoi (554944) | more than 10 years ago | (#7024179)

What effect will this have on the dip to chip ratio? Will this prevent breakage under load? Has anyone measured the performance benefits of salsa compared to sour cream and onion?

Most importantly, will I still need my ThinkGeek 'I am teh Chip Haxx0R' bib?

Bah, this is old! (1, Funny)

ecki (115356) | more than 10 years ago | (#7024212)

Anybody remember the viruses which could travel from floppy to floppy back in the C64 days? You would put an infected floppy next to a clean floppy, and the virus would just hop over! Don't know about the speed though...

(No kidding, there were people back then who told and believed this nonsense ;)

GridComputing (1)

Bluelive (608914) | more than 10 years ago | (#7024228)

Great potential for gridcomputing, just keep adding chips.

This may be of interest to some... (0)

Anonymous Coward | more than 10 years ago | (#7024276)

Schematics here [books-rose.com]

Hard to say what's new here (2, Informative)

kent.dickey (685796) | more than 10 years ago | (#7024277)

The article is a bit vague as to what the innovation really is.

The article immediately made me think of multi-chip modules. Multi-chip modules is an idea which never really caught on in the industry (except for IBM), and I'm not sure how Sun's innovation isn't just a take-off along that idea. Multi-chip modules have failed due to costs since much has to go right to get a multi-chip module that works.

Any practical chip-to-chip connectivity scheme had better have a good rework scheme. If it doesn't, it's just boutique technology that will not affect the industry overall.

Having worked on chips with multi-gigabit pins, a huge problem is resynchonizing the signals. Creating a receiver to align one pin's data with 15 neighbors at 3GHz takes a whole lot more logic space on the die than a small driver (or receiver). The auxiliary logic basically makes shrinking the final driver FET almost meaningless.

Modern chip design is a constant trade-off between features and cost. And what's cheap is what everyone has been doing for years (or is an evolution of that).

Re:Hard to say what's new here (1)

cybermace5 (446439) | more than 10 years ago | (#7024369)

Well, one benefit I can see is that you don't have to drive a huge (in silicon terms) chunk of copper over to the next chip. I guess they have the distances and other parameters figured out so that this capacitive coupling is actually an advantage compared to copper traces.

They could probably do something similar with arrays of laser diodes beaming out the edges of the chips. Then again, maybe the capacitive coupling is better than that in terms of power consumption and speed.

Sun is Dying (-1)

marcomuskus (628509) | more than 10 years ago | (#7024287)

It's a fact, better the start to use Linux or BSD ... OH ! Wait ! BSD is Dying too ...

Fight Club:

morons re-unveil human-to-human connect/survival, (-1, Flamebait)

Anonymous Coward | more than 10 years ago | (#7024294)

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worth reading, again, with feeling.

"It takes a long time to teach the judges, legislators, and public to understand technology. Right now, they're getting a strong dose of "education" on the Internet's threats and harms, and not hearing so much about its potential. Shouts of "piracy" often outweigh consideration of how we might communicate with more open media formats, but judges like Stephen Wilson in the Grokster case are starting to listen through the shouting. We're encouraging more people to think about how the law shapes technological innovation, how the technology itself can foster creativity, and then to do something about it to advance the public interest."--

"The stability of the large world house which is ours will involve a revolution of values to accompany the scientific and freedom revolutions engulfing the earth. We must rapidly begin the shift from a "thing"-oriented society to a "person"-oriented society. When machines and computers, profit motives and property rights are considered more important than people, the giant triplets of racism, materialism and militarism are incapable of being conquered. A civilization can flounder as readily in the face of moral and spiritual bankruptcy as it can through financial bankruptcy."

Yuor speling is teribal, Hemus. (0)

Anonymous Coward | more than 10 years ago | (#7024297)

It's terabit and receivers, Hemos. Not terrabit or recievers.

And its name? (1)

GlassUser (190787) | more than 10 years ago | (#7024325)

Shall we call it Prime Intellect [planetmirror.com] ?

(actually, by the story naming convention, it would be closer to intellect 1, but oh well)

Re:And its name? (1)

zapp (201236) | more than 10 years ago | (#7024437)

shoot, you beat me to it. Good story though.

Re:And its name? (1)

GlassUser (190787) | more than 10 years ago | (#7024605)

I was late too, concerned that someone else would beat me. I enjoyed it though.

Bad math? (4, Insightful)

Quixote (154172) | more than 10 years ago | (#7024332)

I hate it when the hype overshadows the technical details. Here's a snippet from the article:

By comparison, an Intel Pentium 4 processor, the fastest desktop chip, can transmit about 50 billion bits a second. But when the technology is used in complete products, the researchers say, they expect to reach speeds in excess of a trillion bits a second, which would be about 100 times the limits of today's technology.

If a P4 is already doing 50 Gbps (as they say), and this uber-technology will allow 1Tbps (which is 20x a P4's 50Gbps), then how is that "100x the limits of today's technology" ?

<shakes head>

Sun may be ahead in other areas, too (4, Interesting)

Mr. Ophidian Jones (653797) | more than 10 years ago | (#7024350)

Normally I don't pimp Sun, but here's something that makes me think they still have a finger on the pulse of things:
Read about plans for Sun's "Niagra" core [theregister.co.uk]

I understand they hope to create blade systems using high densities of these multiscalar cores for incredible throughput.

There's your parallel/grid computing. ;-)

This reminds me of (2)

BackSpace (41879) | more than 10 years ago | (#7024354)

the Transputer [sbu.ac.uk] . It had 4 available hardware connections and the description of the way the different processors communicate is very similar to what is described by the article.

Of course to take maximum effect of this communication speed in general parallel applications, main memory access would have to be improved. I'd guess these things will have huge on-chip caches.

More on the broader project (4, Informative)

leery (416036) | more than 10 years ago | (#7024360)

IANAEE either, but this made a little more sense to me after I read this Inforworld article [infoworld.com] , which talks about two other aspects of Sun's DARPA-funded project: clockless "asynchronous logic", and building processors with interchangeable and upgradable modules. They absolutely need these busless "proximity" interconnects for the processor modules to communicate at close to on-chip speeds, and the clockless architecture lets them get rid of the bus. Or vice versa... or something like that.

Working prototype computer about six years away, according to the article.

Re:More on the broader project (1)

leery (416036) | more than 10 years ago | (#7024467)

[please strike the "absolutely" from above--i'm not qualified to use that adverb] ...Obviously, announcing this kind of concrete breakthrough is also good for PR, stock price, and future DARPA funding.

Transputer dusted off and presented as new? (2, Informative)

Anonymous Coward | more than 10 years ago | (#7024391)

As usual with alot of Computer Science, this appears to be just an old idea reinvented...the Transputer [smith.edu] ...and about time too!

Reactive Power (1)

snatchitup (466222) | more than 10 years ago | (#7024419)

Now there's something we EE's know about. (Or not...) [ieee.org] We got it wrong in the upper North East with the huge black out.

Looks like it's even used in the tiny chip to chip communications. Basically, to overcome the impotence caused by the little bit of impedance between the chips, we'll add some capacitance (CAPs). Adding the cap's to ground provides reactive power.

BORING (1)

Mooncaller (669824) | more than 10 years ago | (#7024453)

There is nothing new under the Sun. This concept, along with several others like it have been around for at least 15 years.

And then... (1)

Combuchan (123208) | more than 10 years ago | (#7024555)

Ralston Purina [purina.com] will sue for copyright infringement.

This is not new. (1, Funny)

Anonymous Coward | more than 10 years ago | (#7024568)

"Perhaps the beginning of a solution to the lag between memory and interconnect speed versus cpu frequency?"

You mean the problem that everyone outside the PC world already solved? Please people, for your own sake go learn about the alpha architecture. Where all the CPUs connect to other cpus via north, south, east and west. They can all communicate that way, even routing around failed cpus. Then you can start crying when you realize crapaq threw it away.
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