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Stretch Announces Chip That Rewires Itself On The Fly

simoniker posted more than 9 years ago | from the self-reconfiguring-articles-next dept.

Hardware 311

tigre writes "CNET News reports on a chip startup call Stretch which produces the S5000, a RISC processor with electronically programmable hardware so that it can add to its instruction set as it deems necessary. Thus it can re-configure itself to behave like a DSP, or a (digital) ASIC, and perform the equivalent of hundreds of instructions in one cycle. Great way to bridge the gap between general-purpose computing and ASICs."

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Cue Skynet jokes (0)

Anonymous Coward | more than 9 years ago | (#8975098)


Re:Cue Skynet jokes (0)

Anonymous Coward | more than 9 years ago | (#8975133)

"You shall not pass!" LOL! LoTR R0X3NZ Y3R S0X3N5 D00D! WtF?!?!?!?!?!?!? :-\

Re:Cue Skynet jokes (5, Funny)

WwWonka (545303) | more than 9 years ago | (#8975199)

Cue Skynet jokes...GO!

Sooooo this T800 model Terminator walks into a bar with a poodle under on arm and a basketball under the other...

OH boy, Transmeta Part II. (0, Offtopic)

Anonymous Coward | more than 9 years ago | (#8975100)

Je ne se quoi?

Ok froggy. (0)

Anonymous Coward | more than 9 years ago | (#8975286)

I ran your "Je ne se quoi?" through the Google translator [google.com] and I got "I what?".

WTF are you trying to say you stupid frog?

Re:Ok froggy. (0)

Anonymous Coward | more than 9 years ago | (#8975345)

"stupid frog"

Be careful of what you are saying. This guy isn't a frog obviously since what he wrote doesn't mean anything in french.

Re:OH boy, Transmeta Part II. (0)

Anonymous Coward | more than 9 years ago | (#8975379)

French nitpick: It's: "Je ne sais quoi." It means, "I don't know what."

Though I think the phrase you are looking for is "deja vu" (already seen), anyway. It makes more sense with your Subject line.

virus hitting the hardware (5, Insightful)

KDN (3283) | more than 9 years ago | (#8975111)

Can you imagine the virus you could write if you could change the instruction set of the cpu?

Re:virus hitting the hardware (2, Funny)

Neil Blender (555885) | more than 9 years ago | (#8975167)

Can you imagine the virus you could write if you could change the instruction set of the cpu?

Uh, no.

Re:virus hitting the hardware (1)

donnyspi (701349) | more than 9 years ago | (#8975177)

...or if you could tell it to overclock itself? You could melt down someone's PC remotely.

Re:virus hitting the hardware (0, Offtopic)

Tall_Rob (240828) | more than 9 years ago | (#8975204)

Can you imagine the virus you could write if you could change the instruction set of the cpu?


It would destroy such instructions in favor of its new matrix.

/ObKhanQuote :-P

Re:virus hitting the hardware (4, Interesting)

NanoGator (522640) | more than 9 years ago | (#8975237)

"Can you imagine the virus you could write if you could change the instruction set of the cpu?"

Forgive my ignorance, but why would this be any different than the virus you can write with the general purpose CPUs we have today? You could make the machine unreliable, but that wouldn't make for an effective virus distributing machine.

Insightful?! (2, Funny)

CedgeS (159076) | more than 9 years ago | (#8975239)

Wow! The virus could execute arbitrary code! Just like if it could choose which of the existing instructions were executed by another processor. The core part of your virus could run faster, maybe in just one clock cycle!

Re:Insightful?! (1)

Gyorg_Lavode (520114) | more than 9 years ago | (#8975287)

How do you detect a virus that has control of the underlying hardware though...

Re:Insightful?! (4, Interesting)

CedgeS (159076) | more than 9 years ago | (#8975380)

Easy - Say, the extra instructions are supposed perform a matrix convolution. Call extra instruction 1 with some random matrix. If it doesn't calculate the same thing as a slow version run in the regular RISC part you know extra instruction 1 has in some way failed and needs to be reprogrammed. Your virus software and OS etc should never have special instructions and are always run in the regular RISC part.

I highly doubt anyone is planning on making PCs with these. They are designed for being a processor in something like a data logging / control system, surveillance video compression, etc. Your system will probably have no need for virus detection any more specific than other more general regression and test suites it will need during operation.

Re:virus hitting the hardware (0)

Anonymous Coward | more than 9 years ago | (#8975318)

Can you imagine the virus you could write if you could change the instruction set of the cpu?

Yeah, it could convince my Camry a few hundred more horse wouldn't be so bad. . .

Re:virus hitting the hardware (1)

The_Mystic_For_Real (766020) | more than 9 years ago | (#8975364)

You could partially solve this problem by running as a restricted user all the time so that you couldn't change the instruction.

New application-speed records to be set... (4, Insightful)

LostCluster (625375) | more than 9 years ago | (#8975114)

If this doesn't rempresent the death of the megahertz as a processor-benchmark standard, I don't know what will...

Effective application speed was never based on a cycle count alone, because different processors can have better instruction sets for the given application. The main breakthrough here is that this chip leaves "user-definable" space in its instruction set so they can re-optimize the instruction set on the fly. Whatever you're running, its most commonly used functions can almost slide from being code to being "on the chip" and that's sure to speed up the experienced speed.

Yeah, I know its a /. cliche, but... imagine a cluster of these!

errmm... (2, Funny)

torpor (458) | more than 9 years ago | (#8975196)

... earth to slashdoid,

being code to being "on the chip" and that's sure to speed up the experienced speed.

first, where exactly is code run, if it isn't 'on a chip', and second, what? speed up the experienced speed?

you mean, as opposed to something like 'pretended speed', which is what i imagine you were using to measure your rapid desire to let your undoubtedly 'speedy' fingers get through your slashdot post without thinking ...

'experienced speed' indeed...

Well... (3, Informative)

Ayanami Rei (621112) | more than 9 years ago | (#8975309)

This is basically an FPGA married to a RISC processor. So if you have a bit of RISC code that can be simulated using the FPGA portion, and you have enough spare cells to add it, and it takes 10 clock cycles for the FPGA "user instruction" to dispatch, but it takes 200 to do it outright in the original RISC instructions, then you're experiencing a 20 to 1 speed increase for that bit. You speed up the function without overclocking. Actually what you've done is "trade off".

He could have posted clearer, if he wasn't trying for first post.

Re:errmm... (1)

LostCluster (625375) | more than 9 years ago | (#8975337)

first, where exactly is code run, if it isn't 'on a chip', and second, what? speed up the experienced speed?

When a function is defined in code, you have to use multiple processor cycles to complete the function. However, when the funciton is "on the chip", that entire function can be completed in just one assembly-level call to the processor.

"Experienced speed" is of course a pseudo-benchmark because it can't be standardized, and its components highly specialized. It's how fast you can complete a set of particular real-world task without having advance knowledge of what the chip is going to be asked to do. It's how fast the system actually "feels" to the user...

Re:New application-speed records to be set... (4, Interesting)

Stripe7 (571267) | more than 9 years ago | (#8975293)

This looks interesting, at this generation it looks to be dedicated applications. You code for your particular application and use their compiler which restructures the CPU to optimize for that application. What it does not say is if the hardware changes are read/write. If you release a maintenance patch to your application, do you have to swap in a new CPU for optimal performance? If the area is read/write just how many times can you change the CPU instruction set? Can you change the CPU instruction set with something else other than using their compiler? That is using a microcode release that rewrites the CPU. I would not want to load a compiler onto every one of my products.

Beware! (5, Funny)

spudthepotatofreak (649917) | more than 9 years ago | (#8975115)

Give these damn chips awhile to evolve and you'll have borg nanoprobes... Beware the nanoprobes!!

Re:Beware! (0)

Anonymous Coward | more than 9 years ago | (#8975365)

It's not the nanoprobes I'm afraid of, it's the megaprobes :-)

Donald Duck (-1, Offtopic)

Anonymous Coward | more than 9 years ago | (#8975123)

Donald Duck was going to have a SCREAMING ORAGSM frist p0st, but he didn't make it quite in time, but he's havihge a SCREAMING SQUIRMING ORGASM l00king at Da1sy Dcuk pr0n NEways. OMG OMG

so does that mean... (2, Insightful)

hatrisc (555862) | more than 9 years ago | (#8975124)

we can have only one standard assembly language? the hell with java if that's the case.

Re:so does that mean... (5, Informative)

tuffy (10202) | more than 9 years ago | (#8975281)

we can have only one standard assembly language?

That's already here. It's called "C".

Whoa.. (5, Funny)

Anonymous Coward | more than 9 years ago | (#8975127)

Just imagine a Beowulf Clu...oh. Skynet. Right.

Let's not do this one.

Help me! Help me! (0)

Anonymous Coward | more than 9 years ago | (#8975128)

Cue "The Fly" jokes.

yawn ... (4, Insightful)

torpor (458) | more than 9 years ago | (#8975134)

... wake me up when i can buy a thousand of them for $10 a piece ...

[okay, okay, so it'll be -hell- fun to design codecs and other protocols that can switch their chipset dynamically, yeah, but i'd need 1000's of them deployed to have a real reason to do it...]

Re:yawn ... (1)

Tatarize (682683) | more than 9 years ago | (#8975394)

Wake me when I can buy a thousand of them on one chip for a few hundred bucks. Come on... gimme diamond fabbed, multi-layer, super-scaler, dynamicly reprogrammable cpu.

Where did I put that android head?

So, do they have Chippy? (5, Funny)

Neil Blender (555885) | more than 9 years ago | (#8975139)

"I see that you are (insert processor mumbojumbo.) Would you like me to reconfigure my instruction sets?"

Can someone explain? (2, Interesting)

aiken_d (127097) | more than 9 years ago | (#8975141)

How is this different from FPGA's?


Re:Can someone explain? (0)

Anonymous Coward | more than 9 years ago | (#8975214)

How is this different from FPGA's?

It is fast and cheap.. enuf said.

Re:Can someone explain? (4, Informative)

DaHat (247651) | more than 9 years ago | (#8975274)

For the most part, FPGA's you build its code from scratch, you give it it's identity of how it works, what it does and so on.

This chip sounds like a hybrid between an FPGA and a run of the mill general purpose RISC processor. Being based on a RISC instruction set, you code for it as you would a normal processor, however if the compiler sees code which could take advantage of having more CPU support, it could add instructions to the FPGA like portion of the chip to enable better throughput.

The short summery is: FPGA, programmed from scratch. Standard RISC processor: Already has instruction set which you program against.

This could be quite handy for some of the embedded programming I do.

Re:Can someone explain? (1)

Hektor_Troy (262592) | more than 9 years ago | (#8975279)

As far as I can tell, it is different in that you have essentially an FPGA-like chip on the same core as a regular CPU.

Re:Can someone explain? (1)

Valar (167606) | more than 9 years ago | (#8975283)

a FPGA is just a block of logic gates that can be connected after the original manufacture. Typically, they are used to implement simple logic cheaply and easily. This is more of an entire processor designed on a similar principle. I would guess that it includes registers, a clock, bus connection facilities, etc. If anything, this is closer to a CPLD which combines i/o blocks, function cells and interconnection blocks to create somewhat more complicated (and often times sequential, as opposed to combinational) logic.

Re:Can someone explain? (1)

imadork (226897) | more than 9 years ago | (#8975295)

How is this different from FPGA's?

If I read the article correctly, the difference is in the compiler.

When you write code for this processor, the compiler would figure out which operations would fit best in reprogrammable logic, then configures the logic and compiles to this custom instruction set all on its own. At runtime, the custom logic is loaded and the program executes.

A traditional FPGA, while reconfigurable, is normally developed in Verilog or VHDL. Where reconfigurable logic is used in a microprocessor-oriented system, you have two development paths: HDL code for the hardware, and whatever the software goys are using for the software.

The neat thing about this is that their C compiler is essentially doing the hardware coding.for you. I'm much more interested in the compiler than in the chip itself...

Re:Can someone explain? (1)

satguy (713646) | more than 9 years ago | (#8975297)

FPGA is the name of the physical packaging of the IC ("floating pin grid array"), while this item is an IC that can effectively burn new neural pathways and deploy new instructions in whatever packaging it's put.

Re:Can someone explain? (1)

wronskyMan (676763) | more than 9 years ago | (#8975301)

FPGAs are reprogrammed with internal switches; some of them use actual fuses that are blown/fused to make connections. In any case, they probably do not reconfigure as fast as this chip; in addition, IIRC, FPGAs have a limit to how many times they can be reprogrammed.

Re:Can someone explain? (1)

Hast (24833) | more than 9 years ago | (#8975335)

Well it seems rather similar to the Virtex 2 Pro, those have PowerPCs integrated on them. Although they are rather expensive. And while the individual chips may not be all that expensive the boards are.

All in all it seems like these have a developer environment which helps the user port C/C++ programs to this platform. There has been quite a few of those chips / systems before though. It will be interesting to see if this one can take off the ground where the others have failed.

more info (5, Informative)

morcheeba (260908) | more than 9 years ago | (#8975142)

NetworkZone has a product review [analogzone.com] with some more insight. A good quote:

...the [300 MHz] Stretch even beats the Intrinsity FastMath processor running at 2 GHz

Of course, there is no such thing as a universal solution and the Stretch processor does have its limits. One significant area is in "low touch" operations such as network processors. While it can certainly do the relatively simple packet inspection and transformation that switch fabrics and network processors normally handle, it is really much better suited to the heavy-duty calculation- and manipulation-intensive tasks found in "high touch" applications such as video compression. For example, H.263/264 motion estimation is capable of producing very high-quality video from a relatively small bit stream, but requires lots (and lots) of raw processing horsepower. Happily, the Stretch processor is only too happy to oblige, churning out a SAD (sum-absolute difference) operation on a tile-full of pixels for H.263 video in 43 ns (H.264 takes 83 ns).

even more info (2, Informative)

Anonymous Coward | more than 9 years ago | (#8975363)

EE Times has an article here [eetimes.com]. Apparently this chip has a competitor. There's also more details about the chip itself.

(Anonymous because logging in at work)

This is a setback for crypto-land... (4, Insightful)

LostCluster (625375) | more than 9 years ago | (#8975144)

I think we're going to have to move the crypto benchmarks back a step when this tech comes out. Not very many of us have RISC chips that are optimized for MD5 or any of the other popular crypto formulas, but if the typical consumer PC had this technology, we could all effectively have an on-demand RISC for whatever we need at the moment sitting in our PCs.

In short, the time-to-crack using consumer technologies for almost any form of crypto is about to take a step backwards. It won't "break" anything, but the brute force combinations will be able to be examined in a faster time, meaning higher standards will be needed for the same level of protection you have today.

Not surprising, these breakthroughs will always keep coming...

Re:This is a setback for crypto-land... (0)

Anonymous Coward | more than 9 years ago | (#8975198)

Even if this improves the performance of brute-force attacks 1000 fold that will still only reduce the time it takes to brute-force a good key from 5 trillion years to 4 trillion.

hahahahaha ... Worst Math Ever (0)

Anonymous Coward | more than 9 years ago | (#8975272)

Okay... so you're saying it now takes 5 trillion years, and if you could do it 1000 times as fast, it'll take 4 trillion years...


Re:This is a setback for crypto-land... (0)

Anonymous Coward | more than 9 years ago | (#8975226)

shut your face, you stupid karma git. how about i mod my insightful fist in your karma ass?

Re:This is a setback for crypto-land... (2, Insightful)

jsac (71558) | more than 9 years ago | (#8975248)

Luckily it will also immensely speed up encryption times. So, on the whole, probably a gain for the white hats rather than the black hats.

Re:This is a setback for crypto-land... (1)

torpor (458) | more than 9 years ago | (#8975385)

yeah, i could imagine this being more of a boost for crypto than anything else, actually. if you can dynamically hardware-assist certain parts of your bitstream, changing 'code' and 'data' states not just on one side of a set of registers, but on the other side as well, then it is the beginning of a whole new realm of hard crypto ...

i have to wonder what sort of instruction sets they've got running... could I, for example, 'emulate' other architectures on it dynamically? I haven't quite penetrated their market-blurbs yet, but it sure would be nice to know what sort of apps and architectures they've already got running ...

why RTFA? (-1, Offtopic)

Anonymous Coward | more than 9 years ago | (#8975145)

...when you can get people clamoring to get the title of Karma-whore in response to a stupid-ass question or troll?

Keywords in this article. (0)

Anonymous Coward | more than 9 years ago | (#8975154)

startup call[ed] Stretch

As soon as Ti or intel start pumping these out I'll jump onboard but with Stretch as my only source...

Anything more? (4, Funny)

AtariAmarok (451306) | more than 9 years ago | (#8975158)

Is this the only technology they managed to salvage from the android's severed hand? Any interesting gears and motors at all?

How is it possible? (5, Insightful)

dhasenan (758719) | more than 9 years ago | (#8975163)

How can something that normally takes "hundreds of thousands of instructions" be handled in a single instruction? Surely all the same mathematical operations must take place, except for some optimization. Or is it a matter of a certain structure for computation being created in a more permanent fashion rather than being dynamically formed upon demand? Then the operations could be performed in a single cycle. On the other hand, that portion of the processor would become useless to other tasks. Or am I misunderstanding this entirely?

Re:How is it possible? (3, Informative)

Professr3 (670356) | more than 9 years ago | (#8975255)

Say you had to compute a 10000-entry sin/cos table (simple example). The processor would reconfigure itself to perform sin/cos operations in a single cycle (parallel ALUs etc.) and, if there were enough configurable circuits, perhaps multiple sin/cos table entries at once. That's where the speed advantage is - large blocks of repetitious calculations. With a sophisticated enough reprogramming AI, computationally intensive apps like video games could get a huge performance boost.

Re:How is it possible? (2, Informative)

Chirs (87576) | more than 9 years ago | (#8975259)

You hit upon the answer in the latter portion of your post. Most cpus are generalists--they're fast at most things, but aren't optimized for anything. This kind of tech allows you to optimize your cpu for a particular task.

If you have something that needs to do a simple operation on each member of a large data set, the chip could be configured as many tiny simple cores that are just smart enough to do that operation.

Or if you needed to do a complicated math function, you could optimize the cpu for that function.

Of course, it takes a certain amount of time to do the reconfiguration, so it may only pay off for many repetitions or very complex calculations.

Re:How is it possible? (2, Informative)

radish (98371) | more than 9 years ago | (#8975296)

I studied "Custom Computing" as it was called at my university a few years ago. That was based around using FPGAs as the processor, but with the same idea of doing on-the-fly redesign of your hardware to suit the current problem.

The basic idea is to move problems from the time space (i.e. do X then Y then Z taking T time to do it) to the physical space (i.e. do X next to Y next to Z taking S transistors to do so, but only one cycle). So your simple add operation in a regular microprocessor, which fetches the data and runs them through a generic arithmetic unit before putting the result back somewhere would instead have the load, add and store circuitry "hard coded" in actual transistors.

It takes some serious mental acrobatics for a programmer like me, which probably led to my not-so-stellar performance in that class ;) But it sure is interesting.

Re:How is it possible? (1)

Boogaroo (604901) | more than 9 years ago | (#8975303)

Perhaps they mis-worded it.

You can do lots of addition/subtraction instructions to get the result of a single multiplication instruction.

Maybe they meant to say thousands of clock cycles can be reduced to one clock cycle since you can have larger single instructions(i.e. squareroot over pi or something) programmed into the chip that only take one cycle?

Re:How is it possible? (2, Informative)

the morgawr (670303) | more than 9 years ago | (#8975304)

It's a DSP/RISC processor (basically the same thing) with an on-chip FPGA. If you have some particular algorithm, you can put it on the FPGA to get a solution instead of having to use code. (this is a lot harder to explain then I thought it would be....)

Re:How is it possible? (0)

Anonymous Coward | more than 9 years ago | (#8975343)


Hmmmm... (1, Funny)

pmbuko (162438) | more than 9 years ago | (#8975166)

I tried to do something like this once, but I kept running into the problem of differential voltages in the pulse-modulated ion core. I think they must have shunted the positrons through the floating point pathways, thus creating an artificial singularity in which the laws of EE no longer apply.

Re:Hmmmm... (5, Funny)

schon (31600) | more than 9 years ago | (#8975332)

I tried to do something like this once, but I kept running into the problem of differential voltages in the pulse-modulated ion core.

Ahh - that's easy. You should have routed the ion core voltages through a phase discriminator; would have cleared that right up.

I think they must have shunted the positrons through the floating point pathways

No, that would have caused a cascade failure in the deflector array.

Finally (2, Funny)

Anonymous Coward | more than 9 years ago | (#8975168)

I can tell my computer to go fuck itself and it will.

Reduced Benefits for Virtual Machines? (3, Insightful)

SlipJig (184130) | more than 9 years ago | (#8975172)

IANAEE, but I was just wondering if this technology provides greater advantages to unique monolithic apps as opposed to apps targeted for virtual machines such as the JVM or CLR. Those VMs are general-purpose, and maybe apps that run on them would be "invisible" to the hardware reprogrammability... however I don't know how just-in-time native compilation might change that picture. Anyone with knowledge of this stuff care to enlighten?

Re:Reduced Benefits for Virtual Machines? (1)

LostCluster (625375) | more than 9 years ago | (#8975238)

Right now, this product isn't meant for PCs quite yet. Basically, the manufacturer instructions are to write your program in standard C, and then run it through their application which will convert the most-used C functions into a RISC instruction for the chip.

So "virtual machines" is a situation this chip hasn't had to encounter yet. I'm guessing that a PC user would have to throw the switch manually to change which "processor image" is running at any given time...

Not really new technology (5, Informative)

stephenry (648792) | more than 9 years ago | (#8975173)

It's called DISC, Dynamically Reconfigurable-Set Computer. It's existed for a few years now. If I remember correctly, there is a group at Berkley working in the area and have released a few nice papers on it.

Re:Not really new technology (2, Insightful)

wed128 (722152) | more than 9 years ago | (#8975310)

yea, but a working implementation is a long way from a concept paper...

Again? (1)

LostOne (51301) | more than 9 years ago | (#8975174)

At least this one doesn't claim to be bulletproof and be able to adapt to any situation conceivable instantly without loss of information or ability to continue operating. I seem to recall something like that popping up a number of years ago.

That reminds me of... (4, Interesting)

ajiva (156759) | more than 9 years ago | (#8975183)

I remember a project where hardware engineers setup a cpu to modify itself until it learned to do a task by itself. It got to the point where the hardware was doing the right thing, but not because the hardware was reconfigured properly, but because the software was using minute naunances in the electricity flowing through to get the job done. Even the hardware designers had no idea how it could possible be working

Sounds good on paper, but... (5, Insightful)

Anonymous Coward | more than 9 years ago | (#8975213)

...I sense another Transmeta coming on...

Yes sure, rewirable chips would be cool for certain applications, but how does one go about making it deal with multiple applications with multiple needs? You'd over load the CPU with a truckload of specialized instructions - which would probably slow it down. Granted, I see uses in things like mobile phones, but for multitasking machines, a 'Jack of all trades' chip is the way to go.

not quite accurate summary (3, Interesting)

ebrandsberg (75344) | more than 9 years ago | (#8975218)

From what I gathered, this allows the compiler to create an instruction that can do a lot of work in one instruction, NOT for the processor to decide to create an instruction. Think of it this way, if you know you need to do something like an array multiply many times, the compiler could create an instruction for it, and then use it as needed. The key to this is that the instruction set can be optimized on a program basis, so you don't waste gates on SSE2 instructions if you don't use them, etc.

This would compare with FPGA's I believe in that most FPGA applications are fixed once loaded, although I know that there was talk about stargate systems on slashdot (http://slashdot.org/article.pl?sid=03/02/15/16292 37&mode=nested&tid=126)
using FPGA's for general processing before.

Re:not quite accurate summary (1)

Hast (24833) | more than 9 years ago | (#8975393)

FPGAs are not static. They can even be reconfigured during runtime. (Though it takes a lot of time, from the chips point of view.)

Search around for reconfigureable FPGA and you'll find that there is several projects which does this. I know of three such projects of the top of my head (Stargate, RAW, Mitrion) so I would exactly call the idea new.

someone remind me... (0)

Anonymous Coward | more than 9 years ago | (#8975234)

what does CNET, RISC, DSP, and ASIC stand for again?

Re:someone remind me... (1)

AKAImBatman (238306) | more than 9 years ago | (#8975372)


Don't ask.


Reduced Instruction Set Computer


Digital Signal Processing


Application-specific integrated circuit

possibly useful (1)

quelrods (521005) | more than 9 years ago | (#8975242)

It sounds interesting enough that I wouldn't mind buying one to play w/ or port an os to. Their numbers of their 300mhz chip outperforming a 2ghz chips makes sense if the instruction set has been changed for a single purpose. A coworker pointed out that task switching can't be that speedy. So a general purpose chip that can automatically tune itself to a specific purpose is how this comes across. Still, this can be useful.

Interesting points in the article (1)

The_Mystic_For_Real (766020) | more than 9 years ago | (#8975243)

The article seems to imply that it works in manner comparable to having 2 processors. I had a box at home with a dual processor set up, and it had some problems running certain applications and just made things more difficult. It will be interesting to see if this chip works in the same way, as the article seems to say.

PLD's have been around for years. (2, Informative)

dispater124 (725880) | more than 9 years ago | (#8975250)

The concept of a programmable hardware device isn't all that new. And the encoding and encryption they talk about speeding up is a typical application of PLD's. High end routers use similar devices to optimize their tables etc. Kuro5shin has a nice article for beginners. http://www.kuro5hin.org/story/2004/2/27/213254/152

Re:PLD's have been around for years. (0)

Anonymous Coward | more than 9 years ago | (#8975269)

i thought kuro5hin was dead...

FPGA (2, Interesting)

tttonyyy (726776) | more than 9 years ago | (#8975265)

FPGAs have had processor IPs [xilinx.com] available for a while, which, in theory, can be reprogrammed on the fly. But AFAIK, no-one does this. I doubt this will be any different.

Hardware manufacturers that need special hardware operations (IE MPEG-2 decoding) use dedicated, custom hardware for large volume production. Dynamically configurable hardware is expensive for large scales production, and small scale production will likely use FPGA for similar effect. I may be sceptical, but I doubt it'll catch on.

FPGAs with embedded PowerPC processors (1)

janolder (536297) | more than 9 years ago | (#8975371)

Better yet, Xilinx also has FPGAs with up to four embedded PowerPC processors [xilinx.com]. These are the real deal, not IP cores that get compiled into the chip by the engineer. I suppose the difference to the part covered in the story is that the programmable logic can be reprogrammed on the fly, not so with this Xilinx part.

I do wonder how they deal with heat dissipation. :-)

Not too different from what's already available... (5, Informative)

stienman (51024) | more than 9 years ago | (#8975278)

This is evolutionary, not revolutionary. Many chipmakers have offered microcontrollers and microprocessors with FPGA on chip. Often it is an extension of the I/O built into the processor, so it's not much different than an external FPGA on the processor bus. Please note that this is NOT like processors that run on the FPGA itself - these are seperate from the FPGA portion of the chip.

Stretch is different in a few ways:
It pulls the FPGA closer to the core, so that it can be utilized almost as part of the pipeline. I say almost because of the following statement in the article:
Inside the chip, the ISEF is coupled to the rest of the circuit by 128-bit buses and has 32 128-bit registers. It runs in parallel with other areas of the processor, effectively becoming a fully reconfigurable co-processor, and can be reprogrammed for new instructions at any time during operation.

So it's still fairly seperate from the processor core.

But the core itself is high performance (fast clock, a little faster than the average FPGA) and it has a very fast memory bus (again faster than the average FPGA)

The downsides are likely to be:
1) Power cost and dissipation. Since it's a slow clock, the dissipation probably won't be bad, but it's not going into a small portable machine.
2) Time to reconfigure. This isn't meant to be a general processor with task switching. Context and task switching is going to be expensive and if you plan on running two concurrent tasks which both require special instructions the entire processor will likely perform, on average, much worse than it would without the reconfigurable portion. Unless, of course, the processes were created to use the same set of special instructions so the context switch isn't more expesnsive than it is for today's processors.

So they are targetting it correctly, it seems. Specialized areas with, in general, only one task/program running at a time. Multimedia players, for example, would be great here. A digital recorder/player would work well if both the encoding and decoding portions of the code were compiled so the special instructions created wouldn't have to be changed for either application to allow playback while recording.


How will this affect cross-platform development? (3, Interesting)

ezraekman (650090) | more than 9 years ago | (#8975289)

This sounds vaguely like the dream solution for developers. The article says:

"It runs in parallel with other areas of the processor, effectively becoming a fully reconfigurable co-processor, and can be reprogrammed for new instructions at any time during operation."

Does that mean it can handly booting multiple OSes simutaniously? If so, how long before someone writes an app that bridges multiple OSes, allowing the equivalent of emulation, without the emulation? I don't know about the rest of you, but the potential of this chip sounds like a dream come true. And at $35-$100 per chip... it's cheaper than the processor for most systems anyway.

Transmeta (1)

vasqzr (619165) | more than 9 years ago | (#8975300)

Anyone else smell hype and unfulfilled promises?

How long does this chip take to change itself? How often can it do it?

Might make for an interesting SMP situation.

The first processor that can? (5, Informative)

mrplado (736237) | more than 9 years ago | (#8975305)

The first processor that can add to its instruction set while operating? I think there were a few microprogrammed processors in the 70s/80s with writable control store that could do exactly that. Anybody remember PERQ workstations? Now this new gadget appears to be able to extend itself by means of an embedded FPGA, instead of plain old microcode, so it's a bit like the Xilinx Virtex II PRO series (PowerPC core with big FPGA on one chip). The really innovative thing is that you don't have to program the FPGA in VHDL or Verilog, but the C++ compiler takes care of that.

Gaming? (3, Interesting)

shirai (42309) | more than 9 years ago | (#8975312)

One of the best applications for this chip is a programmable Graphics card.

Imagine the optimizations that you could do for the next release of the Doom engine. They could own the market for GPUs that optimizes itself for specific games. Could be amazing.

Woooo (3, Interesting)

Cr3d3nd0 (517274) | more than 9 years ago | (#8975324)

I can just see this processor, mixed with a bit of Mark Tildens analog AI research to really advance Artificial Intelligence. For the uninitiated Mark Tilden discovered that by tying a group of only four or so transistors and sending a regular analog signal through it he could get small robots to walk, and indeed do an amazing number of things, including optimize it's path and even remember it's solution for a small amount of time(about 3 or 4 seconds). Not only that but when given a certain stimulus need (example make them solar powered and have only one are of light they would compete with other bots to gain access to better light. Indeed a lot of the behavior that these little bots produce is so complex and life like that he has spent a long time just documenting behaviour. Now give a set of these bot's circuits the ability to "optimize" the speed of the signal, and a few stimuly and let it play. If the stimulous was for "human approval" some input from a human indicating good or bad.... Heck what do I know, I'm non AI researcher but it always sounded cool to me :-) For more information on Mark Tilden go to BEAM Online [beam-online.com]

Starbridge (1)

Arroc (208497) | more than 9 years ago | (#8975334)

reminds me of Starbridge [starbridgesystems.com] and this [slashdot.org] and this [slashdot.org] previous slashdot stories. I have always been interested in the subject, unfortunately in most of the cases similar products end up as vaporware

FPGAs in general purpose computing (1)

mhocker (607466) | more than 9 years ago | (#8975359)

AKA Where are they now?

It's curious. When I was looking at semi companies a few years back, there seemed to be lots of scrappy startups with reconfigurable dreams. I looked at companies that could take c++ code and turn it into silicon, companies that had tools to integrate IP from multiple providers easily, and FPGA producers that wanted to grow beyond the primarily telecom market that they were in.

The idea was plausible, the market and the VCs (at least in Europe) agreed, and lots of money was thrown at the problem.

But if I look at this company, I can't help but feel that it's a bit of deja vu.

Which begs the question, if reconfigurable computing is such a good idea why has it not become as common as the general purpose CPU? I suspect it's because the general purpose CPU is:

1. cheap
2. well understood
3. cheap

Simply put, it's often cheaper to just write code for one of the myriad existing parts or, in the case that you want to have something that's got a custom core, just have it fabbed.

Am I missing something here?
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