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67 comments

FRST PSOT? (-1, Troll)

Anonymous Coward | more than 7 years ago | (#17818338)

Please?

Summary... (1, Insightful)

Otter (3800) | more than 7 years ago | (#17818444)

IBM got wind of Intel's announcement and rushed out their own. The end.

I was skeptical that there really were people who saw them and wondered "Wow, engineers in both companies made these discoveries today?", but a look at the Slashdot story shows the first comment (in my display, anyway) asking "Two breakthroughs in one day?" (Score:5, Insightful)

Re:Summary... (-1, Flamebait)

Anonymous Coward | more than 7 years ago | (#17818530)

Oh shut the fuck up already. No one likes you. Go away.

It had to happen eventually... (0, Informative)

Anonymous Coward | more than 7 years ago | (#17818584)

...Otter got something *right*!

\Nobody likes a braggart.

What actually happened. (1, Funny)

Anonymous Coward | more than 7 years ago | (#17819028)

Intel got wind of IBM's announcement and rushed out their own. The end.

I was skeptical that there really were people who saw them and wondered "Wow, engineers in both companies made these discoveries today?", but a look at the Slashdot story shows the first comment (in my display, anyway) asking "Two breakthroughs in one day?" (Score:5, Insightful)

Re:Summary... (1)

Fordiman (689627) | more than 7 years ago | (#17821806)

IBM, Intel, it doesn't matter.

When am I going to get something the size of an SD card with processor (ARM, >=200MHz), RAM(>=128M), sound(16 bit full-duplex), video (1024x768x24bit), a nice-sized flash HD(>=2G), and contact-headers for IDE & USB ports?

Re:Summary... (0)

Anonymous Coward | more than 7 years ago | (#17825546)

Well, let's not be overly dismissive --- the comment certainly was insightful by the standards of slashdot.

Answer is clear (5, Funny)

Lithdren (605362) | more than 7 years ago | (#17818492)

Intel developed a time travel device and sent a robot back in time to steal the plans from IBM.

And they tried to kill Bill Gate's mother, but you'd be suprised how difficult that was.

You'd think 640 rounds of ammo would be enough to kill anybody.

John Titor (1)

xero314 (722674) | more than 7 years ago | (#17819138)

You claiming John Titor [wikipedia.org] works (well, will work) for Intel? That would certainly explain a lot.
Next thing you know we will find out that IBM has had this technology for a while and even used it in the 5100. [wikipedia.org]

Re:Answer is clear (1)

humungusfungus (81155) | more than 7 years ago | (#17822526)

Nonono, you're off by an order of magnitude.

640k rounds of ammo ought be enough to kill anybody*.

* Except Chuck Norris.

Re:Answer is clear (1)

ScrewMaster (602015) | more than 7 years ago | (#17822866)

Two orders, actually.

Re:Answer is clear (1)

humungusfungus (81155) | more than 7 years ago | (#17823194)

See, I get my mind on Chuck, and all of a sudden I go stupid. Thanks for pointing that out. :)

Re:Answer is clear (1)

ScrewMaster (602015) | more than 7 years ago | (#17823276)

Well, it just goes to make your point even more, I'd say. I dunno how many squibs get fired off in a typical Chuck Norris flick but it's got to be in the thousands.

Silicon Valley will become K-Valley then? (4, Informative)

namityadav (989838) | more than 7 years ago | (#17818496)

From Intel: High-K Material is a material that can replace silicon dioxide as a gate dielectric. It has good insulating properties and also creates high capacitance (hence the term "high-k") between the gate and the channel. Both of these are desirable properties for high performance transistors. "k" (actually the Greek letter kappa) is an engineering term for the ability of a material to hold electric charge. Think of a sponge. It can hold a lot of water. Wood can hold some but not as much. Glass can't hold any at all. Similarly, some materials can store charge better than others, hence have a higher "k" value. Also, because high-k materials can be thicker than silicon dioxide, while retaining the same desirable properties, they greatly reduce leakage.

Re:Silicon Valley will become K-Valley then? (3, Informative)

exley (221867) | more than 7 years ago | (#17818650)

No. The substrate that these chips are fabbed on is still silicon. The article is somewhat misleading because it's the gate oxide, which is typically made of silicon dioxide, that's being replaced with the hafnium-based high-k material. I'm loathe to site this as a source but since it has pictures, here [wikipedia.org] is a Wikipedia article that will show you the basic structure for anyone unfamiliar.

I also find it interesting that they are using metal gates instead of polysilicon, considering that metal gates were used in the olden days before the switch to poly.

Re:Silicon Valley will become K-Valley then? (1)

DeadCatX2 (950953) | more than 7 years ago | (#17819914)

Uh, the GP never made any claims about the substrate. In fact, GP specifically stated this is the gate dielectric that's being replaced.

So, your statement of "no" makes no sense, because you're agreeing with the GP.

Oh, and the reason they're using metal gates instead of poly, can be found courtesy of RWT, last paragraph of the following link

http://www.realworldtech.com/page.cfm?ArticleID=RW T012707024759&p=3 [realworldtech.com]

Since polysilicon is not compatible with Intel's high-k material, the newer 45nm transistors use a metal gate

Re:Silicon Valley will become K-Valley then? (1)

John Hasler (414242) | more than 7 years ago | (#17820032)

> Uh, the GP never made any claims about the substrate.

The article implies that hafnium is to supplant silicon entirely. The subject line " Silicon Valley will become K-Valley then?" implies something similar.

Re:Silicon Valley will become K-Valley then? (1)

DeadCatX2 (950953) | more than 7 years ago | (#17820248)

Oooh. When you said no, you weren't talking about the GP, but the article.

Re:Silicon Valley will become K-Valley then? (1)

default luser (529332) | more than 7 years ago | (#17830134)

It's not just a "compatibility" problem.

Semi designers have been trying to ditch polysilicon for years. Back when it was introduced, it was an improvement over metal gates, but that's not the case anymore. Since it's still a semiconductor, you get a depletion region on the poly itself. You can ignore this in large processes, but as things shrink it really starts to have an effect.

Re:Silicon Valley will become K-Valley then? (1)

Maury Markowitz (452832) | more than 7 years ago | (#17820374)

I'm curious to know where this leads though. As I understand it one of the largest reasons for abandoning widespread use of GaAs semis was that there was no analog of SiO2. If I am reading these releases correctly, it's the SiO2 that's being replaced by the Ha. So if this is correct, wouldn't a GaAs system using the same methodologies be "doable"?

Forgive my newbie-ness, fab tech isn't my strong suit.

Maury

Re:Silicon Valley will become K-Valley then? (1)

grrrl (110084) | more than 7 years ago | (#17824610)

The ease of growing SiO2 initially made it one of the best features of the Si system which is why billions have been spent to mature the industry - they have now reached the point where the rest of the money and time invested into Si technology still makes Si processing far superior to all other materials systems (in the end, Si is cheap and they already have it all working - changing one thing is much easier than moving to a whole different material system).

Re:Silicon Valley will become K-Valley then? (1, Informative)

Anonymous Coward | more than 7 years ago | (#17821162)

"I also find it interesting that they are using metal gates instead of polysilicon, considering that metal gates were used in the olden days before the switch to poly."

Yup, we used to use metal gates, but the difference in work function between the gate and the silicon caused problems. It gets somewhat confusing, but I'll try to explain briefly. The work function is a basic property of a metal or semiconductor that indicates the distance from the vacuum level to the fermi level of a plain piece of that material. When two materials with different work functions are placed in contact, the fermi levels align, and this can "bend" the conduction bands on the semiconductor. In the operation of a MOSFET these bands are also bent in various ways by voltage applied to the gate, but if the original bend is too large, it would take a huge voltage to move the conduction band to where its needed. This can result in a threshold (or turn on) voltage that is too large to be usable.

When transistors were first developed, there were metals that had somewhat decent work functions, but they weren't great, and since its a basic property of the metal, it was a fixed value, that gave a pretty firm threshold voltage. As the process was scaled down the threshold voltage didn't scale with it. Then someone came up with the idea of using polysilicon for the gates, which solved all the work function problems. Polysilicon is just silicon grown on top of the wafer without the stringent growth conditions, seed crystals, controls, etc. that produce a wafer made out of a single crystal, so it is formed of many small crystals of silicon instead of one. But, since its still silicon, the work function is close to that of the rest of the transistor, and can be adjusted and fine tuned to any work function needed by doping it along with everything else.

However, while polysilicon gates solved the work function problem, they created new problems of their own. They aren't as conductive as a metal, so you get some resistive loss in the gate and an increased delay when coupled with the gate capacitance. You also have a small depletion layer that forms against the oxide when the transistor is turned on, simmilar to the channel that forms on the other side of the oxide. This depletion region effectively adds extra thickness to the oxide, and thus lowers its capacitance. Lowered cap at that point in the transistor means less control over the channel, and reduced performance. You can thin the oxide to make up for it, but that gives you more leakage (the depletion region in the poly will conduct if the oxide leaks anything, so it doesn't help with leakage). High-K materials can also help with this issue, but they can only do so much.

When the switch to polysilicon gates was first started the added resistance was pretty much negligable since the gates were so large, and the depletion region was much smaller than the oxide thickness so it wasn't the dominant factor in gate capacitance. After much scaling, however, the gate resistance is now signifigant and the loss of gate cap is pretty bad. Companies have been working for quite some time to find a metal that would work to replace poly, but its been difficult to find an alloy with a work fuction close to silicon, or that can be adjusted to be close to silicon. Its finally been done, so the next generation or two of processes will see the return of metal gates.

Metal has always been better, its just been too difficult to use metal once the polysilicon trick was developed, but the polysilicon "hack" is starting to break down, so we're forced to go back to metal gates and find some way to make it "work".

Exley, Question (1)

Khyber (864651) | more than 7 years ago | (#17825328)

Ever hear of Ovonic Unified Memory? http://www.ovonyx.com/tech_html.html [ovonyx.com] With this technology, silicon may be put into it's place for memory purposes. Bye, Flash. My only question is, could this be used for processors, given the statement in this link "OUM offers a way to realize full system-on-a-chip capability through integrating unified memory, linear, and logic on the same silicon chip." ? Do you think this would be a better way to go with processor cache, higher densities, less heat, and semi-equivalent access speeds?

Re:Silicon Valley will become K-Valley then? (0, Troll)

Anonymous Coward | more than 7 years ago | (#17818836)

Shut up. How is a high gate capacitance desirable for a high performance transistor?

Re:Silicon Valley will become K-Valley then? (2, Informative)

exley (221867) | more than 7 years ago | (#17818914)

Despite the fact that you decided to go troll on us with how you responded to the parent post, I'll bite since this was something I got to thinking about as well.

Higher gate capacitance means that you can get more charge in the channel for a given gate voltage (Q=CV). This can give both higer currents and a reduced threshold voltage, which are good things.

But higher capacitance, of course, slows things down when you get to thinking about those RC time constants. So, do the benefits of higher capacitance outweigh the negatives? IBM and Intel seem to think so.

Re:Silicon Valley will become K-Valley then? (5, Informative)

Umbrel (1040414) | more than 7 years ago | (#17819408)

The improvement is not about increased capacitance in each transistor channel, that would be bad. The capacitance is scpecifically increased in the gate, that means that the gates can be made thicker (less leakage currents = less power consumption) while keeping (or improving) the values for current and voltaje needed to be applied at the gate and the time for the transistor to switch.

Re:Silicon Valley will become K-Valley then? (2, Informative)

exley (221867) | more than 7 years ago | (#17821678)

The gate itself isn't inherently capacitive, it's the capacitance of the gate/oxide/channel structure that we're talking about, so you can't decouple gate capacitance and channel capacitance. Charge on the gate (which you can think of as the top plate of a parallel plate capacitor) results in equal but opposite charge on the channel (the bottom plate, with the insulating oxide acting as the dielectric).

You are absolutely correct that the point in increasing the thickness of that oxide is to reduce leakage and power consumption. But increasing the thickness of the gate oxide lowers the capacitance of the structure, so they want high-k materials to compensate for this.

Re:Silicon Valley will become K-Valley then? (0)

Anonymous Coward | more than 7 years ago | (#17819416)

Well that's not quite right. While the capacitance/area is larger, the devices are also smaller. This means that the total capacitance will remain more or less constant.

Re:Silicon Valley will become K-Valley then? (0)

Anonymous Coward | more than 7 years ago | (#17819694)

You are correct on the first portion. High-K material means you get bigger capacitor between the metal gate and the silicon, allowing you to make a bigger inversion layer. This has nothing to do with RC delay.


RC delay is the delay due to resistance and capacitance of the data transmission, which are bus lines that run throughout the chip. These are the metal wires that connect on stage of CMOS to the next. the reason we switched to copper is because of the lower resistivity compare to aluminum, and the reason we are using low-K dielectric to surround the metal line is to reduce the parasitic capacitance between those bus lines.


so, it's two separate issues. we want low resistance, low-k for stuff BETWEEN transistors. We want very high-k material for the gate dielectric INSIDE a transistor. Without changing the k-value of the gate dielectric, device engineers has been shrinking the gate thickness down to about 10~20 atomic layers. This cause leakage between gate and silicon, which is wasted heat. By going with a higher-k material, we can now matain the same transistor current driving characteristic without dropping the thickness. In fact, the pdf article show they actually can add more thickness to the gate now because Hf-oxide dielectric makes a better capacitor than SiO2.

Re:Silicon Valley will become K-Valley then? (1)

warrior (15708) | more than 7 years ago | (#17820070)

Um, by definition the gate _capacitance_ is part of the RC network. The grandparent is right in that if Tox was kept constant then the RC delay would go up.

Re:Silicon Valley will become K-Valley then? (1)

exley (221867) | more than 7 years ago | (#17821704)

Right, I was going to say just that before I saw your post. I'm guessing that the capacitance of the interconnect dominates over the gate capacitance in the RC delays? I'm used to the low-speed analog world where we don't worry as much about our interconnect in terms of self capacitance.

Re:Silicon Valley will become K-Valley then? (1)

warrior (15708) | more than 7 years ago | (#17822248)

I'm guessing that the capacitance of the interconnect dominates over the gate capacitance in the RC delays?
 
I'm willing to wager that most of the time it is. To scale (or keep constant) R the metal aspect ratios are ridiculous, resulting in high lateral cap. Either high R or C drowns out the gate cap (but it's still situation-dependent).

These FETs should be great for analog - no gate leakage, reduced short-channel effects should make current-mirrors/sources a pleasure and the high gm won't hurt analog circuits, either...

Re:Silicon Valley will become K-Valley then? (0)

Anonymous Coward | more than 7 years ago | (#17822410)

Yes. Capacitance over the interconnect dominates the RC delay. In the RC delay model, the gate capacitance is treated as a load (imagine you have to turn on the next cascade of CMOS transistors). picture a current source with 2 capacitor in parallel and a resistor in series. 1 capacitor is the parasitic interconnect capacitor. 1 capacitor is the gate capacitor. the resistor is the metal line resistance.

From an analog circuit engineer's perspective, the gate capacitance matters in the RC delay and the engineer will have to make sure not to fan out to too many gates. However, from a device physicist's perspective (which is the perspective of the paper and this whole topic), we don't care. we want to keep the RC delay low on the interconnect level (low-k inter-metal dielectric), while keeping the transistor good on the device level (high-k gate dielectric).

Interconnect capacitance is bad. it's excess load we don't want to drive.

Gate capacitance is good. it's the "good" load we would like to drive.

Re:Silicon Valley will become K-Valley then? (1)

warrior (15708) | more than 7 years ago | (#17819986)

The high-k material doesn't necessarily mean the capacitance of the gate will be higher, that depends on the dimensions of the gate as well as the material. If the thickness of the dielectric was kept constant the cap would go up, but what we're trying to do here is increase the dielectric thickness while maintaining performance. By increasing the dielectric thickness we can put a stop to the quantum tunneling that creates gate leakage. If we did this using the same Si02 gate dielectric it would cause an increase in threshold voltage and decrease in transistor gain. Gate cap is not usually the largest capacitive component on a given route (interconnect, usually). I'm sure there's a sweet spot for transistor performance vs average RC. However, those finite RC contants might be what limits these designs in the end, something a lower impedance connection to VDD/VSS can't do anything about.

Re:Silicon Valley will become K-Valley then? (3, Funny)

Anonymous Coward | more than 7 years ago | (#17819472)

Think of a sponge. It can hold a lot of water...Glass can't hold any at all.

Try holding the glass right-side up.

Re:Silicon Valley will become K-Valley then? (0)

Anonymous Coward | more than 7 years ago | (#17820002)

Wot?
The very worst thing for a fast switch transistor is capacitance.

Future Research Documentation... (1)

frieza79 (947618) | more than 7 years ago | (#17818516)

Wow, they have future documentation on research. Did that research include time travel?!?!

I liked the way the Register put it better (1, Offtopic)

ben there... (946946) | more than 7 years ago | (#17818642)

Well, wouldn't you know it, we just happen to have acquired a rough version of that very presentation. Geeks out there can read up on IBM's breakthrough ahead of time via this PDF [regmedia.co.uk] - a Register exclusive.

Doesn't it suck when someone messes with your timing?
IBM deserves a bit of a jab from the folks at Register whom they fooled for a few days with their "paper release" technology.

Isn't it obvious? (1)

Wicko (977078) | more than 7 years ago | (#17818816)

It is pretty clear that IBM is desperate. Intel has a ton of momentum, and they have to be stopped somehow, even if it means throwing themselves at the rolling boulder. It seems obvious why they would try to reveal their new tech at the same time, when you keep in mind how much of a lead Intel has at the moment.

Re:Isn't it obvious? (2, Funny)

kfg (145172) | more than 7 years ago | (#17819002)

See Swann vs. Edison. Swann demonstrated first. Edison had a personal PR department.

It's all about the marketing. However, in that case the battle was asymetrical, not just in marketing, but in time to market. Having shit on the shelves with your name on it is marketing that's pretty hard to trump.

KFG

Re:Isn't it obvious? (1)

dascandy (869781) | more than 7 years ago | (#17819396)

Also the story of Graham Bell versus the other bloke/gal that invented telephone. Allegedly about 6 hours between each other.

Makes me feel really sorry for the bloke/gal whose name I can't even remember.

Re:Isn't it obvious? (0)

Anonymous Coward | more than 7 years ago | (#17819774)

Especially when there is evidence the bloke filed the patent first, but Bell paid them off to redate his.

Re:Isn't it obvious? (1)

stevesliva (648202) | more than 7 years ago | (#17821160)

It is pretty clear that IBM is desperate. Intel has a ton of momentum, and they have to be stopped somehow
No. Yes. No.

IBM being six months behind Intel in 45nm tech is pretty meaningless unless Intel uses it to somehow grab more Itanium share, which is unlikely. Other than in Power vs. Itanium they're not direct competitors, and even in that arena, it's like calling the Corvettes and Ferraris competitors. Sure, you may end up buying the other thing, but only if you drastically alter your expectations.

Different story for AMD.

)Ep! (-1, Redundant)

Anonymous Coward | more than 7 years ago | (#17818890)

deClined in market I won't bore you

Why Adhere? (4, Insightful)

camperdave (969942) | more than 7 years ago | (#17819964)

... enabling continued adherence to Moore's Law

I don't understand why you would want to adhere to Moore's law. If I were able to make chips 10 times denser, why would I not market that right away rather than waiting for 3-5 years needed to follow the law.

Re:Why Adhere? (0)

Anonymous Coward | more than 7 years ago | (#17820520)

I don't think the problem has ever been that we're intentionally slowing ourselves down so that it can keep up with us, if you know what I mean.

Re:Why Adhere? (1)

noidentity (188756) | more than 7 years ago | (#17820718)

You think Gitmo is bad; breaking the "laws" of the universe really gets you in deep Guano.

Re:Why Adhere? (2, Insightful)

camperdave (969942) | more than 7 years ago | (#17821764)

Moore's law is not a law of the universe. It is merely an average rate of development of an industry. It's like saying cars are 2% more fuel efficient each consecutive year. It wouldn't break any law of the universe to suddenly release an SUV that was 10% more fuel efficient than last year's model.

Re:Why Adhere? (1)

noidentity (188756) | more than 7 years ago | (#17836318)

And similarily, it wouldn't break any law of the universe to suddenly make something go faster than the speed of light (or other such thing considered impossible, if going faster than light is logically impossible), it would simply mean that we were wrong about that "law" of the universe [sciflicks.com] .

But yes, I realize that "Moore's Law" would be better named "Moore's Observed Trend that is cited way more than it deserves".

Re:Why Adhere? (1)

greylion3 (555507) | more than 7 years ago | (#17821300)

If I were able to make chips 10 times denser, why would I not market that right away rather than waiting for 3-5 years

So, you'd rather sell the next-over generation of chips right away and make x billion dollars, than stretch it out over 3-5 years and make 3-5 times x billion dollars, with you being practically guaranteed to stay ahead of the competition the whole time?

That'll go down really well with the CFO.

"Hey, a goose that lays golden eggs ... damn, I'm hungry.."

Re:Why Adhere? (1)

wall0159 (881759) | more than 7 years ago | (#17823142)

...because you'd want to maximise your profit by not selling your latest and greatest until you have to.. supply and demand, you see...

Mac transition to Intel (1)

jsantos (113796) | more than 7 years ago | (#17821102)

Maybe Intel being farther ahead with this technology was a big part of why Apple moved to Intel processors.

Re:Mac transition to Intel (Steve Jobs knew) (0)

Anonymous Coward | more than 7 years ago | (#17822246)

I would be willing to bet my customary amount ($1) that Steve Jobs learned that this was part of the Intel Roadmap when he talked to them a couple of years ago.

Summary (0)

Anonymous Coward | more than 7 years ago | (#17821892)

So let me see if I've got the story straight.

  * Both companies developed the same technique over a period of multiple years.
  * IBM decided to publish their technique as a scientific article.
  * Intel decided to "publish" their technique at a news conference.
  * In response, IBM decided to also hold a news conference.

Did I miss anything?

All I can say is that it must be really annoying to make a simultaneous discovery and if one of them tries to patent it ... well fighting that out is one mess I wouldn't want any part of.

AMD competitive? (1)

ZX3 Junglist (643835) | more than 7 years ago | (#17824584)

Largely, the consumer base has been watching the competition between Intel and AMD. Intel is now leading AMD in die size, with 45nm now ready for green light. From what all the watchers seemed to think, AMD was shaking in its boots with the earlier hints from Intel on the new gate architecture. But, if you'll notice from TFA: no fewer than two AMD scientists worked on this project. What do you think?

What will this do to the price of hafnium? (1)

Richard Kirk (535523) | more than 7 years ago | (#17826450)

I thought I know most of my elements. I had heard of hafnium, but I had no idea where it was in the periodic table. It is in the transitions, towards the bottom left. You regularly hear of some 'breakthrough' semiconductor made from gallium, aluminium, arsenic, tellurium, buckytubes, Higgs bosons and lard, but this is hafnium with our old friend silicon. Not the first thing you might pick when trying to find a replacement for silicon dioxide. It has a large capture cross-section for thermal neutrons...

Which reminded me. Back in the 1930's, gadolinium was found to have a huge capture cross section for thermal neutrons. One of the people who discovered this managed to corner over 60% of the world's supply of gadolinium, but failed to make his fortune ( or so I remember. I have just been searching for some confirmation of this but no luck ). It is found at a few percent with zirconium, so it isn't exactly rare. However, if you happened to have a jar of the stuff on the shelf, you must be wondering what it is worth.

Almost a shame it is true. It would have made a magnificent scam.

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