×

Welcome to the Slashdot Beta site -- learn more here. Use the link in the footer or click here to return to the Classic version of Slashdot.

Thank you!

Before you choose to head back to the Classic look of the site, we'd appreciate it if you share your thoughts on the Beta; your feedback is what drives our ongoing development.

Beta is different and we value you taking the time to try it out. Please take a look at the changes we've made in Beta and  learn more about it. Thanks for reading, and for making the site better!

A Three-Way AMD Opteron Server

kdawson posted more than 6 years ago | from the one-hop dept.

AMD 137

Abdul tips a thin little review up at The Inquirer of the Themis Slice. "The Slice is a three socket Opteron machine with two PCIe slots and two Infiniband 4x ports... Why would you want three sockets rather than four? Easy, latency. Any CPU in a 3S system is one hop away from any other CPU. In a 4S system, you can be two hops away. This adds latency, and more importantly, you take a big hit on cache coherency latency. This kills performance."

cancel ×
This is a preview of your comment

No Comment Title Entered

Anonymous Coward 1 minute ago

No Comment Entered

137 comments

Weird (1)

Major Blud (789630) | more than 6 years ago | (#20215093)

That is one weird looking board. "you take a big hit on cache coherency latency" Isn't this only a problem with NUMA based systems (of which Opteron is)? The article also mentions UltraSparc and PowerPC-64....

Re:Weird (5, Informative)

Anonymous Coward | more than 6 years ago | (#20215165)

This is also a problem on FSB systems, as all CPUs need to snoop the bus for cache coherency information. On Intels dual-bus systems, this information needs to go across busses. The Intel 4 FSB systems are even worse. AFAIK, Opteron is the only x86 chip that would support 6 cores (12 cores with Barcelona) with a single hop.

Re:Weird (1)

CastrTroy (595695) | more than 6 years ago | (#20215247)

Couldn't you build a 4-way,8-way, or N-Way board where there isn't such a latency problem? Where each processor is connected to each other processor. Sure the circuit design would be pretty complex, but if it is such a speed increase, such that 3 processors gives you more power than 4, then it might be worth it. It might be very difficult with 16 + processors, but 4 shouldn't be that difficult. If it is impossible, please explain why.

Re:Weird (5, Informative)

TheRaven64 (641858) | more than 6 years ago | (#20215377)

Yes, it's possible. The main problem in general is that cost scales in proportion to the factorial of the number of nodes. The main problem in the specific case of Opterons is that each chip needs one HyperTransport controller per other CPU. Current Opterons come with up to three HT connections, and you need one for connecting to the PCIe bus, and other peripherals, leaving two for CPU-to-CPU connections.

Re:Weird (2, Interesting)

poopdeville (841677) | more than 6 years ago | (#20215559)

I was under the impression that this latency issue was caused by the fact that there is no positive solution to the utility problem [wolfram.com]. Essentially, each core is connected directly to the other two, in a planar graph. There's no way to connect each of 4 cores to the other three without the connections intersecting, at least if the connections are made on anything topologicically the same as a convex subset of the plane (that is, no planar graph exists).

This can be solved directly by creating chips with multiple planes on which connections can be made, or indirectly by running messages through other cores, at the cost of latency. Then again, I have no idea if multi-layer chips are in production.

Re:Weird (2, Informative)

TheRaven64 (641858) | more than 6 years ago | (#20215713)

Not really, because modern circuit boards are not planes. A modern motherboard is typically 7 layers, with wires in one layer all running parallel to each other. Within a die the utility problem is much more of an issue, but this is largely due to constraints other than those under discussion.

Re:Weird (1)

conspirator57 (1123519) | more than 6 years ago | (#20215823)

Structured ASICs typically have several (7-9 being common) metal routing layers which can and do cross without interconnect on a regular basis. Vias == pillars comprised by layering dots in each layer. crossing is accomplished with other materials which may or may not be removed depending on your expense/yield/dielectric properties needs. The last impacts EM coupling of traces and inter-symbol interference, and by extension speed.

Re:Weird (1)

poopdeville (841677) | more than 6 years ago | (#20216013)

So a specific question: do modern dice have the ability to use multiple planes? I'm referring specifically to those in use by AMD and Intel for multi-core machines. Circuit boards as such aren't really relevant to the issue of interconnecting cores on dice.

Wrong? (1)

Ygorl (688307) | more than 6 years ago | (#20216389)

I'm probably missing something, but you can definitely have a fully-connected planar graph with four nodes. Make a triangle out of three, stick the fourth in the middle of the triangle and connect it out to the other three.

Re:Wrong? (1)

poopdeville (841677) | more than 6 years ago | (#20216617)

Yes, but you're not going to be able to connect the middle core to anything but the other three cores.

On the other hand, I didn't mention that the system bus was a "utility" for the purposes of the problem, so your counter-example is right in context.

Re:Weird (1)

knapkin (665863) | more than 6 years ago | (#20216437)

If you read the link you posted you would see you have misquoted or misinterpreted the utility problem.  Below is a diagram showing how to connect 4 nodes to each of the other 3 without intersection in one plane.  Posted as code because I can't seem to get it to work otherwise.

X---X
|\ /|
| X |
\ | /
  X

Re:Weird (1)

poopdeville (841677) | more than 6 years ago | (#20216851)

The system bus is a "utility" for the purposes of the problem as well. There are two ways to interpret this: first, as a utility problem, since each core needs to connect to four utilities. Or, after a counting argument, as the 5-node complete graph K5, which cannot be embedded in the plane.

Re:Weird (1)

knapkin (665863) | more than 6 years ago | (#20217057)

This is true, if you include the system bus, you have 5 nodes which each have to be connected to the other 4 and you get K5. I was simply responding to the statement that:

There's no way to connect each of 4 cores to the other three without the connections intersecting, at least if the connections are made on anything topologicically the same as a convex subset of the plane (that is, no planar graph exists).

Re:Weird (1)

poopdeville (841677) | more than 6 years ago | (#20217465)

Agreed, your counter-example was appropriate for the context I set up. I assumed that the system bus would be included among the interconnections necessary, but phrased it in a way that made that very non-obvious.

Re:Weird (1)

contrapunctus (907549) | more than 6 years ago | (#20215399)

You'd have to put the processors in a circle or something...

Re:Weird (1)

poopdeville (841677) | more than 6 years ago | (#20215681)

Wouldn't work. See http://mathworld.wolfram.com/UtilityGraph.html [wolfram.com] What you really need is to allow interconnections to go over or under each other.

Re:Weird (2, Interesting)

pla (258480) | more than 6 years ago | (#20215571)

If it is impossible, please explain why.

Problem 1)
Draw four circles on a piece of paper.
Now draw a line from every circle to every other circle without crossing any lines.

Problem 2)
Draw four circles on a piece of paper. Draw two "pins" on each.
Now draw a minimal path between any two circles such that you can only start and stop at a pin, and only one connection can go to a single pin.



You have the right idea for problem 1, that for low-N, you can just route connections through different layers of the board. But that only works for low-N and doesn't generalize (though in fairness, neither does to the "3-CPU" solution).

For problem #2, no real solution exists other than limiting the degree of connectedness to some low number of pins (2 gives the simplest case above single-CPU, a daisy-chain or ring topology), or having centralized signal switching (star topology).

Re:Weird (1)

HaloZero (610207) | more than 6 years ago | (#20216067)

That assumes a two-dimensional topology. PCBs do not suffer that same constraint (e.g. they have more than a single layer to work with). Any side of a six-sided cube is adjacent to any other side, assuming that you have the ability to transport a unit along the interior of the cube. If you took all six processors, and wired them with the same theory, no processor is more than one hop away from any other.

Re:Weird (5, Insightful)

rrhal (88665) | more than 6 years ago | (#20216113)

           x
          /|\
         / | \
        /  x  \
       / .   . \
      x---------x

Re:Weird (0)

Anonymous Coward | more than 6 years ago | (#20216201)

I wish I still had mod points from this morning. You, sir, would get one on 5 of your posts.

Re:Weird (0)

Anonymous Coward | more than 6 years ago | (#20216375)

Very pretty.

And just how do you propose to connect to the memory and other devices? That currently takes the spot of one of your Xs.

BTTF (0)

Anonymous Coward | more than 6 years ago | (#20216631)

Is that a Flux Capacitor?

nothing new (3, Informative)

Exter-C (310390) | more than 6 years ago | (#20215115)

There is nothing new in this product at all, IBM have had this type of server platform (3 socket supported) for some time in the form factor of the x3755.

IBM System x3755 (5, Informative)

OS24Ever (245667) | more than 6 years ago | (#20215143)

Disclaimer, I work for IBM.

The IBM System x3755 [ibm.com] has offered this feature since it came out as well. Instead of the fourth processor card you install a pass through card and it turns it into a three way. We've done a few benchmarks [lionbridge.com] (warning pdf) with the Pass Through card and what it could do between 3CPU and 4CPU operations.

pretty cool ability for a few things.

Re:IBM System x3755 (5, Funny)

Anonymous Coward | more than 6 years ago | (#20215449)

OS24Ever wrote, "Disclaimer, I work for IBM."

You don't say... : p

Re:IBM System x3755 (2, Interesting)

mr_mischief (456295) | more than 6 years ago | (#20216481)

Actually, I've never worked for IBM, and I keep pricing eComStation. I'd kind of like to use that on a system or two. Warp 3 is getting a bit paunchy. I don't want to drop it, though, because then I'd be down to Linux, BSD, Windows, OS X, DOS, and AmigaOS.

Visopsys, ReactOS, OpenSolaris, plan9, Minix, QNX, MMURTL, OpenVMS, Haiku, and some others could serve for utility and novelty in varying degrees, but I already have plenty of software for OS/2.

Yes, I'm an avid system collector. If you have hardware or software that's old, obsolete, and quirky, I probably want it.

The article had me at 'three-way'. (1)

FatSean (18753) | more than 6 years ago | (#20217111)

Something about weird non-standard systems gets me going. I think I want this system. Dunno what for or why,but I want it.

Re:IBM System x3755 (1)

OS24Ever (245667) | more than 6 years ago | (#20217117)

For the record, I used OS/2 before I worked for IBM, and not after I worked for IBM. I got a Win95 machine. Though at the time we still had end users on OS/2. I think it got pushed out when they started Y2K-ing things as a desktop OS. I was a heavy 1.3/2.x user, even ran a BBS on it in the early 90s, Maximus was the name if I remembered right.

Re:IBM System x3755 (1)

afidel (530433) | more than 6 years ago | (#20215919)

Rerun the test with the HP having 15K disks and I might not dismiss the results. Oh and I hate that SPECjbb2005 doesn't require financial disclose, jobs per $ and jobs per watt are the only things that really matter.

Re:IBM System x3755 (1)

Zak3056 (69287) | more than 6 years ago | (#20216769)

Rerun the test with the HP having 15K disks and I might not dismiss the results.

They actually did address this in their benchmark document:

Configuration Exception
Due to backorder shipping delays from HP on the 144GB SAS 15K RPM hard drives the 72GB SAS drives
were deemed an acceptable substitute. The SPECjbb2005 workload tool does nothing to exercise the hard
drive and writes no data to it.
As a result, this configuration exception was determined to be immaterial to the
performance results addressed in this study.


So while I would still take it with a grain of salt, I wouldn't dismiss the results out of hand... usually if someone is trying to game the numbers, they don't come out and address the problem so directly.

A three way, huh? (0)

Anonymous Coward | more than 6 years ago | (#20215147)

Can't post that one on Youtube [youtube.com].

What is this article about? (2, Funny)

WFFS (694717) | more than 6 years ago | (#20215181)

Sorry... I tuned out after 'A Three-Way'.

Too bad it was two other guys (1)

spun (1352) | more than 6 years ago | (#20215803)

I guess you shouldn't have tuned out, now look what you're stuck with.

Twice.

CoProcessors? (4, Interesting)

tji (74570) | more than 6 years ago | (#20215197)

Wasn't AMD also talking about licenses or agreements with other companies to allow for different types of coprocessor chips to be used alongside their processors?

There is some interesting potential in that realm.. Crypto accelerators for VPN, SAN, or other devices. Multimedia encode/decode accelerators (encode 1080P H.264 in real time?). Inevitable video game acceleration devices (physics co-processor, accelerated NIC chip, 3D GPU offload processor?).

Those would be even more interesting in home-user oriented Athlon64 boards. Multi-socket opteron boards are out of my price range.

Re:CoProcessors? (2, Insightful)

DigiShaman (671371) | more than 6 years ago | (#20216731)

That's why we have buses to open up expansion possibilities.

For example, we have NIC chips that offload TX checksum processing, Audio accelerators (Creative X-Fi), 3D GPU cards (nVidia and ATI cards), and physic cards (ASUS brand AGEIA card). The only reason you want a dedicated socket is for extremely fast and wide IO to RAM. So far, only the GPU has come close to needing that but hanging just fine with the PCI Express interface.

What would you do... (5, Funny)

Tackhead (54550) | more than 6 years ago | (#20215235)

...with a million dollars?

> Why would you want three sockets rather than four? Easy, latency. Any CPU in a 3S system is one hop away from any other CPU. In a 4S system, you can be two hops away. This adds latency, and more importantly, you take a big hit on cache coherency latency. This kills performance."

Lawrence: Three chips at the same time, man.
Peter: That's it? If you had a million dollars, you'd use three sockets at the same time?
Lawrence: Damn straight. I always wanted to do that, man. And I think if I worked at AMD I could hook that up, too; 'cause I hate motherboard layouts with latency.
Peter: Well, not all layouts.
Lawrence: Well, the type of chips that'd triple up on a board like that would.
Peter: Good point.
Lawrence: Well, what about you now? what would you do?
Peter: Besides three chips at the same time?
Lawrence: Well, yeah.
Peter: Idle.
Lawrence: Idle, huh? Peter: I would relax... I would sit on my ass all day... I would idle.
Lawrence: Well, you don't need a million dollars to idle, man. Take a look at that fourth chip: it's two hops away, don't do shit.

Re:What would you do... (0, Offtopic)

realdodgeman (1113225) | more than 6 years ago | (#20215429)

You don't need a million dollars. I know Microsoft is a rip-off, but 1 million for the Xbox 360? Don't think so... But then again they use PowerPC CPUs.

Re:What would you do... (0)

Anonymous Coward | more than 6 years ago | (#20216869)

Only on Slashdot would the expression "three way" be used in reference to CPUs and get guys excited too.

Mac OS X on this machine... (2, Funny)

andrewd18 (989408) | more than 6 years ago | (#20215249)

Any CPU in a 3S system is one hop away from any other CPU.
So... if I run Mac OS X on this box, can we call it an iHOP?

Where's the specs? (2, Interesting)

achbed (97139) | more than 6 years ago | (#20215297)

There's no reference to this board/blade anywhere on the manufacturer's site. The only thing I can find is that this guy saw this board at a conference and took a shot and wrote a really short article about it. Ok, so a 3-way is a bit of a novelty, but good luck getting it to work. Isn't most microcode on the processors designed with 1, 2, or 4 way in mind? And isn't the cache coherency microcode embedded (at least in part) on the processors themselves? So setting up a 3-way using current processors would actually increase latency and error-checking, correct? IANAPD, but this seems like a dead end.

Re:Where's the specs? (1)

mistahkurtz (1047838) | more than 6 years ago | (#20216027)

well... i called the mfr, and they don't sell this stuff to you and i. their gear is put on air craft carriers, and destroyers, where they have specialty applications written. take the article for what it truly is, an fyi on some interesting technology, and leave it at that.

Threesome (2, Funny)

macdaddy (38372) | more than 6 years ago | (#20215301)

So what kind of doe will this Opteron Threesome run me?

Same latency with 4 processors (4, Interesting)

Laxator2 (973549) | more than 6 years ago | (#20215331)

The article states that with 3 processors one gets better performance, latency wise, because in a triangle configuration any processor cache is just one hop away. You can have 4 processors in a tetrahedron configuration and still have any processor one hop away. Of course it will take 3 hypertransport connections per processor just for the internal communications, so a 4th connection is needed for at least one processor to connect to the northbridge. The quad-core Opteron will have a maximum of 4 hypertransport connections, is that right ?

Re:Same latency with 4 processors (1)

pla (258480) | more than 6 years ago | (#20215649)

You can have 4 processors in a tetrahedron configuration and still have any processor one hop away

Ignoring the physical trace-routing issues, you can have N fully connected nodes as long as every one has a N-1 connections (ie, a dedicated link to every other node), plus you need at least one bus-drop somewhere.

In practice, all those connections need to physically connect somewhere, making more than a handful of fully-connected processors all but impossible.

Re:Same latency with 4 processors (1)

Chris Burke (6130) | more than 6 years ago | (#20215893)

The quad-core Opteron will have a maximum of 4 hypertransport connections, is that right ?

Will have, yes, once both chip and socket support it. The current socket only supports 3 HT links.

Re:Same latency with 4 processors (5, Informative)

default luser (529332) | more than 6 years ago | (#20216419)

Yes, the quad-core chips will have the fourth link. In addition, the chips will be able to split their 16-bit HT links into dual 8-bit HT links, allowing for 8-way CPU configurations without hops (8 x 8-bit HT links per socket). In reality, this is the reason why AMD is pushing the new HyperTransport 3.0: so they can cut the bus lines to 8 without sacrificing too much bandwidth.

Check it out here. [realworldtech.com]

Re:Same latency with 4 processors (1)

Mac_D83 (616934) | more than 6 years ago | (#20216969)

Yeah you can have the same latency if you connect them like this:

P---P
| X |
P---P

The caveat is you need 3 connections per cpu instead of 2.

The 2 connection setup would look like this:

      P
    / \
  P---P

Cheers
Michael Mc Donnell

Re:Same latency with 4 processors (1)

Jeff DeMaagd (2015) | more than 6 years ago | (#20217375)

So far that I know, the AMD CPUs that have three external HT links are the 8xx series Opterons, which gives up to eight physical processors with a maximum of two hops. I haven't heard of one with four external HT links. The 8xx series Opterons are bloody expensive.

3 is a magic number! (0, Flamebait)

wwmedia (950346) | more than 6 years ago | (#20215459)

so 3 is better than 4?

is this AMDs way of saying "oh look we cant make a proper quad core system like intel so we just make 3 the magic number! and everyone will buy our marketing technobable crap"

Re:3 is a magic number! (1)

Ngarrang (1023425) | more than 6 years ago | (#20215607)

so 3 is better than 4?

is this AMDs way of saying "oh look we cant make a proper quad core system like intel so we just make 3 the magic number! and everyone will buy our marketing technobable crap"
Anything is possible. The real question is, what is AMD capable of selling. Sure they can add 1 more hypertransport controllers as some of the others posters have mentioned, but what does that to the cost of the chip? Sometimes, you have to slower to go faster. Or, in this case, you need fewer to do more.

Re:3 is a magic number! (1)

WaXHeLL (452463) | more than 6 years ago | (#20215715)

Quad Core? We're talking about multiple CPUs, not multiple cores.

Re:3 is a magic number! (1)

kabloom (755503) | more than 6 years ago | (#20216497)

You wouldn't want a 16 processor computer?

4 cores per chip (providing 3 unused HTs), by 4 chips.

6-way systems (1)

crow (16139) | more than 6 years ago | (#20215543)

This reminds me of some 6-way systems that I'm told Data General used to sell. They took two 4-way systems, and used one of the processor slots on each as a bridge between the two boards.

4 way? (0)

Anonymous Coward | more than 6 years ago | (#20215561)

Yep 4-way lines don't fit on a 2-dimensional plane, without crossing each other. But who said, we have a single 2-dimensional plane?

Re:4 way? (0, Redundant)

JamesRose (1062530) | more than 6 years ago | (#20215839)

x.........x
...........
.....x.....
...........
.....x.....

Re:4 way? (1, Informative)

Anonymous Coward | more than 6 years ago | (#20216403)

As I understand it, this is more analagous to a chemistry problem than a topographical one. You can consider each CPU as, say, an oxygen atom, with two available HT "bonds" (three minus the one required for PCIe/etc). You can't get four oxygen atoms to mutually bond with each other, no matter what geometry you try.

ROOTER (1)

Bob-taro (996889) | more than 6 years ago | (#20215575)

Opening sentences FTA:

Themis Computer has developed a breakthrough in distributed computing for mission-critical systems. By functionally disaggregating commercial computing resources and housing them in a standardized footprint, purpose-built enclosure, the Themis Slice Architecture provides resilience with superior thermal and kinetic management. This open and modular design allows for spiral technology refresh, extending computing infrastructure investments for complete lifecycle management.
I admit this article is probably just over my head technically, but did anyone else read this and think of ROOTER [mit.edu]? I mean, what is "kinetic management" in a computer? Maybe they spin the CPUs through the air instead of blowing air over them. That might explain "spiral refresh technology" as well.

Workarounds (1)

imgod2u (812837) | more than 6 years ago | (#20215609)

Isn't this only a problem if the OS doesn't manage the NUMA architecture well? Surely there is an OS out there smart enough to recognize separate processors with separate memory regions and assign physical addresses appropriately....

hard to justify (5, Funny)

aapold (753705) | more than 6 years ago | (#20215629)

I mean how to convince the wife that we need a three-way?

Re:hard to justify (2, Funny)

swb (14022) | more than 6 years ago | (#20215717)

Especially when you haven't shown her the value in a two-way yet.

Re:hard to justify (2, Insightful)

pimpimpim (811140) | more than 6 years ago | (#20215931)

tell her it will mean less hops in general, and she might be fine with it.

(sorry about this)

Multi core (2, Interesting)

jshriverWVU (810740) | more than 6 years ago | (#20215711)

Curious if it can take multi-core cpu's. Having a 3way system with dual core opteron's sounds really nice.

think three-dimensional (1, Insightful)

Anonymous Coward | more than 6 years ago | (#20215967)

Any CPU in a 3S system is one hop away from any other CPU. In a 4S system, you can be two hops away. This adds latency, ...

How about a tetrahedron for four CPUs?

Re:think three-dimensional (1, Informative)

Anonymous Coward | more than 6 years ago | (#20216197)

They are talking specifically about the Opteron. Each CPU has two links. You'd need three links from each CPU to form a tetrahedron.

Not as good as it sounds (1)

sunderland56 (621843) | more than 6 years ago | (#20216239)

This architecture might be good for server applications - i.e. lots of instances of a single-CPU task.

However, it doesn't work that well for large apps that get parallelized across multiple CPUs. It turns out that most code, and most compilers, are good at splitting tasks in two - or in powers of two - so having three CPUs is no faster than having two.

Re:Not as good as it sounds (1)

Namlak (850746) | more than 6 years ago | (#20216561)

However, it doesn't work that well for large apps that get parallelized across multiple CPUs. It turns out that most code, and most compilers, are good at splitting tasks in two - or in powers of two - so having three CPUs is no faster than having two.

The third processor can run supporting thread(s) that control the "worker" threads. Let alone support processes such as network, I/O, or anything else in the OS - leaving the two CPUS (and their caches) wide(r) open for application crunching.

Re:Not as good as it sounds (2, Informative)

dlapine (131282) | more than 6 years ago | (#20216741)

Ok, so it's not for HPC systems. I'm betting that the number of servers/server farms out there may make this attractive for the non hpc users, if the 3 way is significantly cheaper than a 4 way. If you can get this on a blade, you get a 50% increase in CPU power for non-parallel tasks.


Hmmm, now that I think about it, a three way box might be really interesting for some HPC loads as well. The low latency is a really big issue for some codes, and the three way could be more scalable (with some hand coding and profiling) than a 4 socket box with non-uniform latencies. The would apply to MPI code written and optimized for specific tasks- not the simple parallelization that some compilers can do. There's a significant number of HPC users who are happy running non-parallel code on hundreds of dual socket systems who might be able to scale fairly easily to 3 way systems. Actually, the code is parallel, to the extent that it runs on both cpus, but these particular users don't want the network latency for MPI code, even on fast networks. They could scale to three way with little loss of performance on one of these.

Hmmm, a third thought occurs to me. A 3 socket system might also be really,really useful for codes that are I/O intensive- let the traditional mpi code run on the first two cpus and let the third handle OS tasks, network operations and high performance filesystem operations. The latency is less of a value in this case, but simply keeping the OS from interrupting the 2 cpus running MPI could be a big win as well. Call it 2N+1 computing.

Ok, I admit it- I like options when it comes to designing systems to meet the needs of different users.

Re:Not as good as it sounds (1)

tomstdenis (446163) | more than 6 years ago | (#20216957)

This is so bullshit I don't know where to begin. GCC is a single threaded application, you can invoke parallel builds with ANY NUMBER of jobs, be it 1, 2, 3, 4, 5, ..., whatever.

So with a 3-way box you'd just use something like -j3 or -j4 to distribute load. unless they're dual cores than -j6 or -j7 would do.

Tom

Is this new? (1)

thatskinnyguy (1129515) | more than 6 years ago | (#20216369)

I'm kinda new to enterprise servers. In the picture it looks as though each CPU has its own bank of memory. If so, is that efficient or not?

It's interesting that (1)

porkchop_d_clown (39923) | more than 6 years ago | (#20216583)

people are more surprised by the 3 CPU sockets than they are by the IB ports.

I thought IB was dead - replaced by 10gigE?

Re:It's interesting that (1)

keeboo (724305) | more than 6 years ago | (#20217047)

I thought IB was dead - replaced by 10gigE?

Doesn't IB have lower latency than that?

I've thought of this (1)

Burpmaster (598437) | more than 6 years ago | (#20216985)

I thought a while ago that AMD, specifically, should create a 3-core processor. Why? Because they can call it the TriAthlon!

940??? (1)

486Hawk (70185) | more than 6 years ago | (#20216997)

From the picture the sockets look to be of the 940 type. Why not make an L1 version of this so you can at least get DDR2 or Barcelona running.

Could be marketed to China (1)

wikinerd (809585) | more than 6 years ago | (#20217155)

A 3-way server could sell better than 4-way ones in China, as the number 4 in China is associated with death.

Re:Could be marketed to China (0)

Anonymous Coward | more than 6 years ago | (#20217403)

A 3-way server could sell better than 4-way ones in China, as the number 4 in China is associated with death.
... and the number 3 is associated with sex.
Load More Comments
Slashdot Account

Need an Account?

Forgot your password?

Don't worry, we never post anything without your permission.

Submission Text Formatting Tips

We support a small subset of HTML, namely these tags:

  • b
  • i
  • p
  • br
  • a
  • ol
  • ul
  • li
  • dl
  • dt
  • dd
  • em
  • strong
  • tt
  • blockquote
  • div
  • quote
  • ecode

"ecode" can be used for code snippets, for example:

<ecode>    while(1) { do_something(); } </ecode>
Sign up for Slashdot Newsletters
Create a Slashdot Account

Loading...