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MIT Focuses on Chip Optimization

CowboyNeal posted more than 7 years ago | from the quality-control dept.

Education 30

eldavojohn writes "MIT's Microsystems Technology Laboratories is focusing on the manufacturing of chips as the variables that affect chip quality become more and more influential. From one of the researchers, "The extremely high speeds of these circuits make them very sensitive to both device and interconnect parameters. The circuit may still work, but with the nanometer-scale deviations in geometry, capacitance or other material properties of the interconnect, these carefully tuned circuits don't operate together at the speed they're supposed to achieve.""

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In Soviet Russia (0, Offtopic)

jombeewoof (1107009) | more than 7 years ago | (#20258477)

variations fluctuate you!!!

Really though, this could be interesting enough if they come out with crazy fast desktop processors.

Re:In Soviet Russia (4, Insightful)

Plammox (717738) | more than 7 years ago | (#20258505)

It's more likely they'll contribute to increasing the yield from each manufactured wafer, making the maybe not so crazy fast desktop processors cheaper. Also, the material and chemical usage will decrease per "good" cpu die, so there's an environmental angle here, which isn't bad either, I suppose.

Re:In Soviet Russia (2, Insightful)

Plammox (717738) | more than 7 years ago | (#20258561)

Just RTFA. It's about RFID chip optimization. But at the 65nm node it's relevant for general CMOS designs as well, including CPU die.

Re:In Soviet Russia (0)

Anonymous Coward | more than 7 years ago | (#20258649)

So have you RTFA yet Plammox?

Re:In Soviet Russia (2, Funny)

Plammox (717738) | more than 7 years ago | (#20258799)

Sorry for my bad english, I meant RTFA in the past tense.

Re:In Soviet Russia (1)

tygerstripes (832644) | more than 7 years ago | (#20258737)

It's about RFID chip optimization.
No, no it really isn't. Most RFID chips are manufactured on a much larger, cheaper scale than 65nm, so none of this research would be relevant there.

Not just lithography (5, Informative)

cannonfodda (557893) | more than 7 years ago | (#20258487)

This isn't really that new. There are folk who have been looking at characterising nano-scale variability for years, and there is a LOT more to it that just the fluctuations introduced by lithographic limits. Glasgow uni's device modelling group [] . What's odd is that these guys are estimating the fluctuations based on mathematical models when there is pretty good data available for the 65nm technology node already.

Re:Not just lithography (1)

tool462 (677306) | more than 7 years ago | (#20258787)

Agreed. It would be interesting to see the actual paper, since--based on what's in this article--they haven't seemed to uncover anything remarkable.

Right. (2, Informative)

lheal (86013) | more than 7 years ago | (#20259001)

We've been doing that kind of stuff at Illinois [] for a while.

Re:Not just lithography (1)

moeinvt (851793) | more than 7 years ago | (#20259353)

"This isn't really that new. . . "

The article is extremely short on details, but it sounds very similar to what IBM has done in the area of "statistical timing" over the last couple of years. []

Re:Not just lithography (1)

keithjr (1091829) | more than 7 years ago | (#20264051)

Indeed. Simulating and optimizing for process faults is often accomplished as a form of Monte Carlo testing [] , where a stochastic sweep is done over various possible process faults to determine the likelihood that transistor parameters like gain or threshold voltage come out as expected. This is often done at the analog design level as a necessary simulation step.

I couldn't find much on the web about this besides a patent from 1994 [] .

Just to clarify (3, Informative)

tygerstripes (832644) | more than 7 years ago | (#20258597)

This work is for RFICs (communication chips), not your 10-Core Hyperon or whatever. More importantly, what they're doing is indirectly modelling the correlation between various electrical properties of the micro-components in order to optimise design stability prior to manufacture. This has no direct impact on the manufacturing process, but does impact on more fabrication-robust design.

Ultimately this will have a limited impact on your desktop's Giggerhurts, somewhere way down the line, but it's nothing you'll notice and, for most of us, nothing we'll really understand. Unless the mathematical basis of chip-fab optimisation is your field, this isn't going to mean much.

Re:Just to clarify (2, Insightful)

Paradigm_Complex (968558) | more than 7 years ago | (#20258637)

Ultimately this will have a limited impact on your desktop's Giggerhurts, somewhere way down the line, but it's nothing you'll notice and, for most of us, nothing we'll really understand. Unless the mathematical basis of chip-fab optimisation is your field, this isn't going to mean much.
There's plenty on /. that won't affect me personally (nor the vast majority of slashdotters). This doesn't lessen our interest in the matter. Perhaps plenty of slashdotters don't understand this now, but having been exposed to this the subject matter may garner some of our interests. Don't underestimate the value (or interest in) information, irrelevant of how useless it may seem.

Re:Just to clarify (1)

tygerstripes (832644) | more than 7 years ago | (#20258689)

You're probably right; I guess I'm just anticipating the crapflood of kids who want to know when it'll ramp up their frame-rate (which, of course, it won't). It doesn't help that the story is vague enough to give that very impression, and knowing how many people love to RTFPhysorgA...

Maybe I'm just getting old, but there seem to be an awful lot more Ritalin-kids on /. these days. Maybe I'll emigrate to

Re:Just to clarify (1)

bigstrat2003 (1058574) | more than 7 years ago | (#20258935)

You left out "Get off my lawn."

Re:Just to clarify (3, Informative)

imgod2u (812837) | more than 7 years ago | (#20261303)

This affects digital chips more than you think. Process variations are a huge problem as we get to smaller and smaller feature sizes. While analog circuits are much more sensitive to variations in threshold-voltage, capacitance and resistance (and cross inductance), keep in mind that all digital circuits are still analog. They are simply interpreted as 1's and 0's.

With this in mind, consider a digital circuit that's driving the output voltage from the voltage of a logical 0 (let's call it 0V) to logical 1 (let's say, 5V for early TTL lovers). That voltage isn't going to rise instantaneously. The time it takes to go from 0 to 5 volts will depend on:

1. The various capacitances of the circuit, both parasitic and device capacitance.
2. Resistance in various circuit elements.
3. Cross-inductance.
4. Threshold voltages for all of the transistors.

Having an accurate model to statistically predict these variations will allow chip designers to better estimate the speed of their digital circuits. So if the target goal of a chip is 10 GHz, they can know, before they commit to silicon, roughly how many chips in a batch will meet that target speed.

Other factors also play in as we get to lower and lower powered chips. With a VDD of 1.0V or below (as in ultra-low-voltage chips), cross-inductance, capacitance on the power rails, etc. can actually affect the stability of a digital circuit. Noise is injected that can turn a voltage that was meant to be a logical 0 into a logical 1. With modern chips turning voltages in regions of the chip on and off, the di/dt problem comes in. Without accurate predictions as to the impedances across the chip, reflections on the power rails can cause a voltage that's higher than VDD and, if the transistors weren't designed conservatively (to meet power and speed goals), they could burn out.

harder on designers (4, Interesting)

drakyri (727902) | more than 7 years ago | (#20258755)

This isn't really anything new - shrinking design processes always make life harder for designers. Each design process (.25 um, 90 nm, etc.) has a set of rules about things - for example, how close interconnects can be to each other without causing interference.

The ruleset for quarter-micron was maybe forty pages. The ruleset for 90 nm was the size of a small phonebook. I don't even want to think about what the rules for 65 or 45 nm must look like.

Re:harder on designers (1)

Narkov (576249) | more than 7 years ago | (#20258781)

At what point does the cost of refinement and R&D this process demands outweigh the benefits of increased yield?

Re:harder on designers (3, Interesting)

John Betonschaar (178617) | more than 7 years ago | (#20258791)

Exactly. As a matter of fact I work for a company (not mentioning which, my boss wouldn't appreciate it) that develops software to migrate chips to smaller technologies, detects/fixes design-rule violations, detects/fixes litho hotspots, that kind of stuff. It is used by many well-known names in the IC industry. We've been in business for more than 10 years already, so this hardly sounds as something new.

Re:harder on designers (1)

imgod2u (812837) | more than 7 years ago | (#20261365)

I'm actually curious. Are you at Synopsys or Cadence?

Re:harder on designers (1)

John Betonschaar (178617) | more than 7 years ago | (#20264379)

No, neither of those 2, but good guesses ;-)

Re:harder on designers (1, Funny)

Anonymous Coward | more than 7 years ago | (#20259127)

The 65nm one is not much bigger than the 90nm one but it is in a vault like out of Mission Impossible and it has dry ice smoke flowing over it.

The 45nm one is like the 2 dimensional prison in Superman II that Zod and his chums get banished into. Except it has greem-screen text characters on it like in the Matrix. And the 2001 music plays whenever you see it.

News? (1)

Colin Smith (2679) | more than 7 years ago | (#20258797)

Shouldn't this be a technical paper in an electrical engineering journal?

Re:News? (1)

gamepro (859021) | more than 7 years ago | (#20260219)

From the article: "The researchers published their results in two papers in February and June. They also presented a paper on the modeling of variation in integrated circuits at this year's International Symposium on Quality Electronic Design." Indeed they are!

monkeys (4, Funny)

stranger_to_himself (1132241) | more than 7 years ago | (#20258843)

I read the title as 'MIT Focuses on Chimp Optimization.'

Thought maybe they'd been having trouble recruiting.

Re:monkeys (1)

Gospodin (547743) | more than 7 years ago | (#20260077)

They figured out a way to generate all of Shakespeare using a finite number of monkeys on typewriters. But it still takes an infinite amount of time.

Re:monkeys (1)

andphi (899406) | more than 7 years ago | (#20260307)

Maybe they should tweak that process so that an infinite number of monkeys can produce results in finite time, then get them working on HURD.

Re:monkeys (1)

PPH (736903) | more than 7 years ago | (#20265095)

That's chips. CHIPS! Not chimps.

As in Fish and Chips.

I love science like this! (1)

killmofasta (460565) | more than 7 years ago | (#20272139)

I really *love* science reporting like this:

1. The "Symposium" was "March 26-28, 2007" ( this is OLD news )

2. The MIT Team presented an invited paper that has *no* Abstract
        "Variation (Invited Paper)"Duane Boning, et al"

3. The paper they presented from the article is for consumer electronics, at 65nm scale, which is basically yesterdays processor technology, ( they should ask AMD and Intel about *their* experence in 65nm fab, although they are working on digital computing silicon and not RFIC chips for digital televisons )

4. The problem they are working on is a constant battle, which everyone fights every time they shrink the channel size

Keep in mind, that silicon is *the most expensive real estate on earth*. The last time I heard about a breakthrough is when they started applying "Khachiyan's breakthrough, applying an approach known as the ellipsoid method to linear programming" to chip layout. now... what exactly is MITs contribution? Not much said, so SHOW ME THE PAPER.
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